TL16C550C: Is it possible to connect this part to IO memory bus interface of the ADSP-2181 ? Is additional logic needed and if so what?

Hi Vassil,

Vassil Jordanov said:

After checking the timing requirements of the part I found that the microcontoller system interface (Fclkout=32MHz) did not meet timing requirements in parameters: td4,td5,td7,td8,th5,th6 and th7.

Short answer is you probably can make it work.

I was able to interface our UART devices with an Arduino mega, I just did everything in the millisecond scale instead of the nanosecond levels. You essentially just have to set up the input pins (Address pins, CS, ect). to the correct logic level then set IOR/IOW to read or write to the parallel pins. You don't need it to be done super fast in the nanosecond time frames like how the datasheet shows. At the end of the day, it's basically a bunch of AND gates tied to the inputs checking threshold levels. 

My main question is, why did you choose the TL16C550C device? I usually try to steer customers to just use a microcontroller/processor with UART embedded in it already. If you have to use an external UART, why not use the most modern one we have (TL16C750E)?

-Bobby

Hi BOBBY,
I understand that if the interface to the TL16C550C (ACE) is implemented with GPIO ports such as those in the ARDUINO MEGA,
there will be no problem.
Unfortunately, this is not the case in our case. Since we don't have free GPIO ports, our idea is to connect the ACE directly to the system IO memory interface of the microcomputer ADSP-2181, which operates at Fclkout=32MHz.
We will use the microcomputer system signals /RD, /WD,
addresses A0-A2, from signals A7-A10 and /IOMS i will work out /CS2 for ACE  and data D8-D15.
Then reading and writing to the ACE registers will happen
automatically after executing one instruction of the microcomputer. For example the read would be ar=io(UART_ADDR0..UART_ADDR7) and the write
io(UART_ADDR0..UART_ADDR7)=ar. Then the sequence and times of appearance of the address and control signals
are strictly determined by the microcomputer.
We can only manage the duration of the /RD and /WR signals from 6.6ns to 225ns with a step of 31.25ns.
Right now I'm confused by the discrepancy
of the following time parameters (I consider only the case when /ADS = 0):
1. td4, td5, td7, td8 - these are the times to establish valid addresses and CS to active /WR and /RD: according to your documentation
the requirement is 7ns min. , and on the microcomputer this time is 3.8ns min.;
2.th3, th4 - these are hold CS and valid address after /WR: 10ns min required, and on our microcomputer it is 4.8ns min;
3. th6 - hold chip select after /RD: required 10ns min., a on the microcomputer 4.8ns min;
4. th7 - valid address hold after /RD: 20ns min. is required, and in the our microcomputer it is 4.8ns min;

I don't know how I could satisfy these times from the datasheet of the ACE.

If you can tell me how to satisfy these timing requirements of the TL16C550C I would appreciate it!
Regarding your question about why we chose the TL16C550C. The answer is because we optimize the price of our products and price of this integrated circuit is the most attractive.

With respect:
Vassil

Hi Vassil,

Vassil Jordanov said:

If you can tell me how to satisfy these timing requirements of the TL16C550C I would appreciate it!
Regarding your question about why we chose the TL16C550C. The answer is because we optimize the price of our products and price of this integrated circuit is the most attractive.

This is going to be on of the rare situations where I try to steer customers away from a certain device (the TL16C550C). We've recently did a redesign of this device because the original design was no longer being supported by our fab process (old factory shut down and new factory can't make the old design). I've seen some customers having issues with the newer designed part, we're still trying to debug what is going on with it (issue is hard to reproduce but when it occurs the processor/mcu gets stuck in a loop due to 550C's INT not clearing). If you absolutely have to use the 550 dataset, I would consider looking at a competitor device like NXP's SC16C550 or Maxlinear's ST16C1550.

-Bobby