DS90UB949-Q1EVM: Question about signal timing - UB948/UB949

Philip Bacera

Part Number: DS90UB949-Q1EVM

Tool/software:

We have a scenario where the UB948 deserializer is connected to an oLDI 2 channel 1920x720 display, so the horizontal data is split into even/odd 960 pixels. The display has the following parameters:

Question: when setting up a test pattern generator on the UB949 serializer - the clock frequency and the horizontal period has to be doubled? The serializer will then split the data into even and odd pixels itself? Could I kindly request that you could write a patgen test script for such screen? The UB949/UB948 pair uses dual-link connection. Thank you.

11 months ago

0 Miguel Bolante 11 months ago

TI__Mastermind 19645 points

Hi Philip,

Depending on the display specifications, sometimes it will be shown as "per port" in which using dual configuration would imply doubling the horizontals and therefore doubling the PCLK as well. The vertical parameters may stay the same.

In this case, we are looking at the following specifications:

Total Horizontal Width =1984
Total Vertical Width = 741

Active Horizontal Width = 1920
Active Vertical Width = 720

Horizontal Back Porch = 20
Vertical Back Porch = 8

Horizontal Sync Width = 24
Vertical Sync Width = 8

Horizontal Front Porch = 20
Vertical Front Porch = 5

PCLK will be determined by the total vertical and horizontal parameters assuming refresh rate is at 60 Hz,
PCLK = 88.21 MHz

I will help with the script you need by referencing Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G), please give me one business day to work on this.

Best,

Miguel

+1 Miguel Bolante 11 months ago in reply to Miguel Bolante

TI__Mastermind 19645 points

Hi Philip,

Please refer to this file below regarding the appropriate register writes for bringing up the PATGEN from the SER:

Fullscreen # 949 EVM PatGen Script Example.py Download

# 949 EVM PatGen Script Example

# On SER:
import time
import sys

# System dependant variables - adjust according to system 
UB949 = 0x18        # 949 I2C Address
UB948 = 0x68        # Remote 948 Address

def pollstate():
    count=0
    board.WriteI2C(UB949,0x23,0x80)
    board.WriteI2C(UB949,0x24,0x80)
    mask = int('11111',2)
    state = board.ReadI2C(UB949,0x24,1)
    while (state & mask) != 27:   #27 = 5'b11011
        time.sleep(0.01)  #10ms delay
        state = board.ReadI2C(UB949,0x24,1)
        count = count +1
        if count == 10:
            print "Error: Serializer is not in Normal state"
            return(1)
    
    board.WriteI2C(UB949,0x23,0x0)
    board.WriteI2C(UB949,0x24,0x0)

def initsequence():

    board.WriteI2C(UB949,0x03,0xDA) # Set I2C passthrough
    
    linked = 0
    retry = 0
    mask = int('10000000',2)
    while linked == 0:
        STS = board.ReadI2C(UB949,0x5A,1)
        if ((STS & mask) != 0):
            linked = 1
            print "Deserializer Detected"
        else:
            time.sleep(0.1)
            retry = retry + 1
            if retry == 10:
                print "Error: No Deserializer Detected"
                return()

    board.WriteI2C(UB948,0x4A,0x01) # Disable OLDI outputs on 948 to prevent screen glitches from appearing during the init process 

    ##### Init A Sequence

    # Errata #2, 3, 4
    board.WriteI2C(UB949,0x5B,0x03) # Force dual FPD-Link, disable reset on PLL frequency change 

    # Errata #7
    board.WriteI2C(UB949,0x16,0x02) # Adjust BCC watchdog timer to minimum

    state_error = pollstate()  # Poll 949 state machine prior to applying init B errata

    if state_error == 1:
        return()

    ##### Init B Sequence

    # 0x64 = 0x05
    board.WriteI2C(UB949, 0x64, 0x05) # Enable Color Bars PATGEN Pattern

    # 0x65 = 0x04
    board.WriteI2C(UB949, 0x65, 0x04) # Select Internal Timing

    # 0x66 = 0x03
    # 0x67 = 0x0B
    board.WriteI2C(UB949, 0x66, 0x03) # PGCDC1
    board.WriteI2C(UB949, 0x67, 0x0B)

    # 0x66 = 0x04
    # 0x67 = 0xC0
    board.WriteI2C(UB949, 0x66, 0x04) # PGTFS1
    board.WriteI2C(UB949, 0x67, 0xC0)

    # 0x66 = 0x05
    # 0x67 = 0x57
    board.WriteI2C(UB949, 0x66, 0x05) # PGTFS2
    board.WriteI2C(UB949, 0x67, 0x57)

    # 0x66 = 0x06
    # 0x67 = 0x2E
    board.WriteI2C(UB949, 0x66, 0x06) # PGTFS3
    board.WriteI2C(UB949, 0x67, 0x2E)

    # 0x66 = 0x07
    # 0x67 = 0x80
    board.WriteI2C(UB949, 0x66, 0x07) # PGAFS1
    board.WriteI2C(UB949, 0x67, 0x80)

    # 0x66 = 0x08
    # 0x67 = 0x07
    board.WriteI2C(UB949, 0x66, 0x08) # PGAFS2
    board.WriteI2C(UB949, 0x67, 0x07)

    # 0x66 = 0x09
    # 0x67 = 0x2D
    board.WriteI2C(UB949, 0x66, 0x09) # PGAFS3
    board.WriteI2C(UB949, 0x67, 0x2D)

    # 0x66 = 0x0A
    # 0x67 = 0x18
    board.WriteI2C(UB949, 0x66, 0x0A) # PGHSW
    board.WriteI2C(UB949, 0x67, 0x18)

    # 0x66 = 0x0B
    # 0x67 = 0x08
    board.WriteI2C(UB949, 0x66, 0x0B) # PGVSW
    board.WriteI2C(UB949, 0x67, 0x08)

    # 0x66 = 0x0C
    # 0x67 = 0x08
    board.WriteI2C(UB949, 0x66, 0x0C) # PGHBP
    board.WriteI2C(UB949, 0x67, 0x08)

    # 0x66 = 0x0D
    # 0x67 = 0x14
    board.WriteI2C(UB949, 0x66, 0x0D) # PGVBP
    board.WriteI2C(UB949, 0x67, 0x14)

    # 0x66 = 0x0E
    # 0x67 = 0x19
    board.WriteI2C(UB949, 0x66, 0x0E) # PGCDC2
    board.WriteI2C(UB949, 0x67, 0x19)

    board.WriteI2C(UB948,0x01,0x01) # Digital reset to restart AEQ 
    time.sleep(0.1) # Allow time for 948 to relock 
    board.WriteI2C(UB948,0x4A,0x00) # Enable OLDI outputs on 948

initsequence()

Please let me know if you have any questions.

Best,

Miguel

0 Philip Bacera 11 months ago in reply to Miguel Bolante

Prodigy 25 points

Miguel, thank you so much, I will give it a try and report back if it doesn't work.

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DS90UB949-Q1EVM: Question about signal timing - UB948/UB949