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PCA9306: PCA9306DCTR problem consultation

Part Number: PCA9306

Tool/software:

Hi TI Team,

1. Can PCA9306 be suitable for PHY-MDC application? The customer MDC clock signal rate is 3.9MHz.

2. At present, because the 2.5V IO pins of FPGA are not enough, the 1.5V IO of FPGA chip is connected to the RSTN and MDC pins of PHY chip after level conversion through PCA9306DCT. The measured results show that the high level amplitude of PHY_RSTN can reach about 2.5V after level conversion. However, the high level amplitude of PHY_MDC is only about 1.8V, the schematic diagram is as follows. Please help analyze it, thank you.

  • Hi Ken,

    1. Yes, see 9.2.2.3 of the data sheet.

    2. I do not see "the 1.5 V IO" shown. I presume you mean the SCL2/SDA2/Vref2/EN side is 1.5 V. If so, note that data sheet recommends for Vref2 >  Vref1 + 0.6 V.

    SCL2 can be 2.5 V if pulled up to 2.5 V, SDA2 can be 1.8 V if pulled up to 1.8 V. If no pull ups, the SCL2/SDA2 sides can clamp to Vref1 voltage levels, thanks.

    Best Regards,

    Michael.

  • Hi  Michael,

    As described in the datasheet, VREF1 supports 1.2V-3.6V, VREF2 supports 1.8V-5V. In our application(as described by Ken),VREF1 voltage VCC_DDR3  is 1.5V, VREF2 voltage is 2.5V, satisfying Vref2 > Vref1 + 0.6 V.

     The PHY_RSTN signal connected to pin 6 has been pulled up to 2.5V, and the PHY_MDC connected to pin 5 has also been pulled up to 2.5V.After PCA9306DCTR level shifting,PHY_RSTN signal voltage has 2.5V, but the PHY_MDC voltage is only 1.8V, which is lower than the expected 2.5V level value, please analyze the reason why the PHY_MDC signal is only 1.8V.

    thanks.

  • When PHY_MDC is 1.8 V, then a current must be flowing though R362, which means that some device must be sinking that current. Is there a voltage drop between pins 5 and 4? Is there a voltage drop over R587? Is anything else connected to PHY_MDC_F or PHY_MDC?