Tool/software:
Hi TI Team,
1. Can PCA9306 be suitable for PHY-MDC application? The customer MDC clock signal rate is 3.9MHz.
2. At present, because the 2.5V IO pins of FPGA are not enough, the 1.5V IO of FPGA chip is connected to the RSTN and MDC pins of PHY chip after level conversion through PCA9306DCT. The measured results show that the high level amplitude of PHY_RSTN can reach about 2.5V after level conversion. However, the high level amplitude of PHY_MDC is only about 1.8V, the schematic diagram is as follows. Please help analyze it, thank you.