TIC12400-Q1: abnormal at ADC input mode

Hello Ethan,

You are correct, this is due to the leakage current with 0mA (+/- 110uA max).  I'll explain the issue with the following example.

The leakage current comes from the Analog MUX pass FET gate bias circuit that is used to connect the enabled INx channels to the ADC for measurement one at a time.  This leakage current is only active on an INx channel when the MUX is actively connecting it to the ADC which is typically 24uS and specified as tADC in the datasheet.  This is essentially equivalent to enabling a pullup resistor to VS that is between 100k-200k in value for 24us when the measurement is being made.  Typically this is absorbed with the current source or sink current when it is a non-zero value.

There is also a resistor divider on the input to the ADC that steps down the voltage to a safe level that is within the ADC range.  The total input resistance is specified as 240k, which means that each resistor is essentially 120k.  This too is only connected to the INx pin during the moment of measurement, but this is in parallel with external restive loads to GND during the moment of measurement.

Typically there is a low pass filter on the INx pin for ESD protection that includes a series resistor and shunt capacitor and therefore an equivalent circuit would look something like the following figure.

The voltage measured by the ADC will depend on the external components connected to the INx pin.  With a completely open pin (i.e. with no filter components) the only path for the leakage current to flow is through the internal resistor divider at the input to the ADC.  During this time, the ADC will see a voltage that is greater than the 6V max ADC code 1023 (0x3FF)

When there is a capacitor added to the INx pin (such as with the ESD filter), the capacitor will charge for 24us while the MUX is actively connecting it to the ADC, and discharge for the remaining duration of the polling cycle.  Without any pulldown resistance or other voltage source to charge/discharge the cap, the capacitor will only discharge through parasitic resistance on the board and may not reach a completely discharged state.  This results in some DC offset voltage and is dependent on the capacitor value, and the polling cycle time.  The following scope is from adding a 15nF cap to same board from the previous measurement.  Note there is a 48ms polling cycle time for this test.  This cap reduces the pulse amplitude to 130mV peak-to-peak, but established a 0.4V common mode voltage.  The ADC returned a value of 89 (0x59)

Adding an external 100k pulldown resistor to the INx pin provides a discharge path to remove the common mode voltage and further reduces the leakage current pulse amplitude.  The ADC now returns a code of 20 (0x14).

Zooming in on a pulse shows the pulse duration correlates to the tADC spec time in the datasheet that is typically 24us.

The initial observations provided of an ADC value between 29-31 is consistent with my example data, but with slightly different circuit components that result in slightly different ADC values.

So, to your question, you will need a capacitor to absorb (decouple) this leakage current, and some form of discharge resistance to prevent the cap from establishing some DC offset. I hope this helps you understand how the device is working.

Regards,

Jonathan