Tool/software:
Hi Team,
The customer uses DP83867IRRGZT with RGMII 1000Mbps.
They aim to adjust the timing using only the delays caused by the pattern on the PCB, without using clock shift modes.
How much internal delay do the TX line(TX_D[3:0], TX_CLK, TX_CTRL) and RX line(RX_D[3:0], RX_CLK, RX_CTRL) signal lines have within the IC package?
They are trying to design the pattern length taking into account the internal delay of the IC package.
Best Regards,
