TCAN4550-Q1: TCAN

Hi Tanushree,

You are not required to use a SPI frequency greater than 10MHz.  The maximum supported SPI frequency is 18MHz, which just means you should not try to use a SPI clock frequency greater than 18MHz.

The maximum size of MRAM is 2kB (2048 bytes) with address range 0x8000 to 0x87FF.

Here are some links to additional resources that contain information that may be helpful to you.

TCAN45xx Software User's Guide (Link)

M_CAN User's Manual (Link)

TCAN455x Clock Optimization and Design Guidelines Application Report (Link)

Regards,

Jonathan

Hello Jonathan,

If we increase the SPI frequency greater than 10Mhz, observed panic in the intialization time. What is the reason for the panic? how to make it work in 18Mhz?
with 10Mhz, we get only 2k messages per second. how to increase the performance? 

Hello Tanushree,

The TCAN4550's max supported SPI clock frequency is 18MHz.  The only other limitation to this is a requirement that the OSC (crystal) clock frequency to be at least 2MHz greater than the SPI clock frequency.  Because the TCAN4550 is designed to work with the standard CAN crystal frequencies of 20MHz and 40MHz, the device should work with 18MHz SPI using either a 20MHz or 40MHz crystal.  If however, the crystal frequency was less than 20MHz, then the max SPI frequency will need to be reduced as well.  For example, if a 16Mhz crystal was used, then the max SPI clock frequency would be 14MHz.

Since my expertise is with the TCAN4550 device level specifications and not with Linux, I'm not sure what causes the "panic" condition in the Linux driver.  I don't know if this is monitoring for a SPI error, or if there is some other limitation in the driver code or processor you are using that creates this condition, but the TCAN4550 does not set any sort of Panic Status.  The device does check for a variety of SPI related errors, mostly due to an incorrect number of bits in a SPI read/write transaction, and too many or too few 32-bit words of data in the transaction based on the "length" field of the SPI header.  I don't know if the device is setting the SPI error flag when the frequency is increased above th10MHz due to poor signal integrity, and if so if the driver is then calling this a "panic" condition.  But I find this unlikely and that the 10MHz limitation is some sort of limitation in the software or processor.

Because all CAN TX and RX message data must be passed through the SPI bus, the overall efficiency and time needed to pass the data through SPI is a limiting factor.  The TCAN4550 supports multi-word SPI read/write transactions for consecutive registers and MRAM memory locations.  This allows the device to receive a single 32-bit header word that contains the read/write op code (0x41 or 0x61), the starting address, and the "length" or number of 32-bit words of data to either read or write in the transaction.  Then the Chip Select (CS) signal should remain low while all data is transmitted without additional idle times or address headers for each register or 32-bit address word location.  This is also sometimes referred to as "burst mode" in some documentation and reduces the idle time and overhead data on the SPI bus to improve efficiency.  The TCAN45xx Software User's Guide discusses this and the datasheet provides a 2 word Read and Write example in the SPI Read and Write figures where 64-bits of data are transmitted and the Length field is set to 2. 

I don't know if the driver you are using is taking advantage of this burst mode communication, or if it is sending a new address header for each 32-bit word of data.  You may need to do some analysis on your SPI bus and driver code to determine if there are any adjustments you can make to improve the efficiency.

The overhead of the processor itself can also add to the overall delay time, so you should try to determine if there are any additional delays or improvements that are coming from the processor's ability to transmit or receive messages as quickly as possible. 

Regards,

Jonathan