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DS320PR1601: Redriver

SHEKHA SHOUKATH
Intellectual 510 points
Part Number: DS320PR1601

Tool/software:

Hi,

Is it okay to route REFCLK between two GND planes?

Thanks and Regards,

Shekha Shoukath

  • 0
    TI__Mastermind 18745 points

    Hi Shekha,

    Can you clarify what you mean by "between two GND planes"? Do you mean that part of the REFCLK line is routed to an internal PCB layer that is between two GND layers?

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Intellectual 510 points

    Hi,

    REFCLK signal is given to a clock buffer to generate 8 clk signals.

    REFCLK from x16 MCIO connector to clock buffer is routed in top layer, while the signals from clock buffer to endpoint connectors are routed in inner layer.

    inner layer is between two ground planes.

    is it okay to route so?

    Thanks and Regards,

    Shekha Shoukath

  • 0 in reply to SHEKHA SHOUKATH
    TI__Mastermind 18745 points

    Hi Sheka,

    The redriver does not use the 100 MHz PCIe REFCLK so I do not have personal experience with nonstandard routing of the clock signal. Our general guidelines say that it is better for high signals to stay on one layer if possible, in order to avoid impedance changes from the different ground planes and the vias that are required to transition from surface layers and inner layers. The REFCLK has a lower operating frequency than the PCIe data lines but it is also vital for PCIe clocking throughout the system and should be kept as clean as possible from disturbances.

    The clock buffer is installed on the top layer, and for the output signals to be routed into the inner layer, I assume there would be signal vias and perhaps some length of traces still on the top layer. So going by the common guidelines from both my experience and what I have read in PCB design material, then it may be better to avoid such a situation if possible, because transitioning the signal from the buffer to the inner layer could introduce problems. If there is no other choice then it would be extra important to backdrill and ground-stitch the vias to reduce the impact of the impedance changes.

    I suggest that you ask the applications support team of the product line (if TI product) or the company responsible for your clock buffer, they should have more direct experience with clock output signal routing.

    Best.

    Evan Su