TCAN4550: SPI Clk speed of TCAN4550

Sukmin Hong

Prodigy 160 points

Part Number: TCAN4550

Tool/software:

Hello, TI Team.

I am using TCAN4550 for my system with STM32H series MCU.

and in the datasheet of TCAN4550, there is max sck rise/fall time of 10ns. (trsck, tfsck)

But in my system, when I checked with sck rise/fall time with oscilloscope, as below tr/tf are about 8~9ns.Almost to Spec.

Will it be any problem?

There is no damping R or cap in the spi sck line between MCU and TCAN4550. SPI Lines are directly connected.

Main clk 40Mhz is very clean.

Our FW Engineer says that there are some missing datas and some garbage data comes out from CAN Line.

So I'm looking into whether it might be related to the HW issue.

Thanks.

10 months ago

+1 Jonathan Nerger 10 months ago

TI__Mastermind 33030 points

Hello Sukmin,

The rise/fall times and frequency are linked due to the shorter bit period at higher frequencies. Therefore, if you were operating at the max frequency of 18MHz, then you would need a rise/fall time of at least 10ns. If you operate at a lower frequency with a larger bit period, then you can have a slower rise/fall time. The waveforms you show look OK and should not cause any problems as long as the setup and hold times are satisfied to ensure the bits are sampled correctly. But as you say, these are very clean waveforms.

To verify if the CAN message data is getting corrupted during the SPI write to the TX buffer, I would suggest trying to read back the data in the TX buffer memory to see if matches what was written. If the CAN message data doesn't match, then this would not likely be due to the SPI interface.

Regards,

Jonathan

0 Sukmin Hong 10 months ago in reply to Jonathan Nerger

Prodigy 160 points

Thanks, Jonathan. I always appreciate your kind and detailed answers.

0 Jonathan Nerger 10 months ago in reply to Sukmin Hong

TI__Mastermind 33030 points

You're welcome.

Regards,

Jonathan

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TCAN4550: SPI Clk speed of TCAN4550