SN65DSI84: SN65DSI84

Hi Yasar,

Here are my comments:

1) Add a 220nF cap to ground on the EN pin. This si to slow down the edge and meet the startup timing requirements.

2) Using a REF clock is recommended as this will provide a cleaner clock.

3) Why do you need a voltage translators from 1.8V to 1.8V?

4) resistors on main link path should be 0201 package. Don't put our device in parallel with another path. This will cause major reflections on the high speed traces.

Yasar Maheen Seenath said:

Do we really need to use external reference clock here, as the datasheet says as "OPTIONAL".

Also, we are supplying D-PHY differential clock.

Are these 2 clock's different? OR either one is required for normal operation? Please clarify.

Yes its possible to use either. I recommend using the REF clock as the clock signal will be much cleaner resulting in a better PLL lock. In my experience, the DSI clock coming into the device tends to go across cables and traces which impacts the signal integrity of the clock which makes it harder for the PLL to lock onto. Using an external clock will mitigate future PLL unlock issues.

If the DSI clock signal is clean at the pins of the DSI84 using the DSI clock is not a concern.

Yasar Maheen Seenath said:

Here one 1.8V refers to SoC power rail and the other one refers to sn65dsi84 rails.

I used as an isolation purpose to avoid those signal flow between SoC and sn65dsi84, before the SoC is fully powered/operational.

Do you have any concerns with this implementation?

No concerns, just curious

Yasar Maheen Seenath said:

We will populate these resistors only in the absence of sn65dsi84 chip, to get direct mapping of DSI lanes on the Carrier board.

Make sure any stubs associated with these bypass resistors are as small as possible to mitigate reflections. Please share layout for review when the board is ready.

Yasar

The schematic itself looks ok.

Thanks

David