TCAN4551-Q1: CANFD Bus Transmit and Receive Frame Loss

Hello Wang,

The RX FIFO 1 Full and RX FIFO 0 Full bits of the MCAN Interrupts register 0x1050 (bits 6 and 2).  This means that the device is unable to receive new messages and will either overwrite or reject new messages until the RX FIFOs have empty buffer elements available.

It appears you are trying to receive CAN messages faster than your processor is able to read and acknowledge them through the SPI bus.  You will need to determine how long it takes for your processor to fully process a RX message through the SPI bus from the notification or interrupt that a new message has been received to the final acknowledgement in the RX FIFO Acknowledge registers (0x10A8 and 0x10B8).

Increasing your RX FIFO depth can add some margin if messages are received in a burst, but on average, you can't receive CAN messages at a regular interval that is faster than you are able to process them through the SPI bus.

Regards,

Jonathan

Thank you for your guidance on communication reception. What could be the possible causes of data loss during transmission?

Hello Wang,

I was looking at how you configured the MRAM and how many elements you have configured for the different types (SID/XID Filters, RX FIFOs and Buffers, TX Buffers and TX Event FIFO, etc.) and I think your allocation exceeds the available memory in the device.  Some of the register values are missing from your list, so I can't be sure and you should check the configuration to ensure that the total bytes used are less than 2048.

It looks like you are trying to enable a TX Queue of 32 elements each with the maximum 64 byte data field and this is the last set of elements in your MRAM.  When the memory address exceeds the maximum field, the device automatically wraps around to the beginning of the MRAM address field.

Overlapping memory sections also may occur without directly realizing it. A read or write to the MRAM address space wraps around to the start of the MRAM after the last address of the MRAM. For example, on the TCAN45xx, there is 2 kB of MRAM, occupying address 0x8000 to 0x87FF. If a user attempts to read or write to register 0x8800, this is the same as a read or write to 0x8000. So it becomes critical to make sure that the MRAM memory is not over-allocated.

If you are overlapping your memory, then you will overwrite your first elements (SID filters, RX Buffers, etc.) and this can lead to both RX and TX errors so please verify your MRAM allocation.

Otherwise, with message transmission, the device will follow the CAN Arbitration protocol and try to send the message at every opportunity until it is successful.  When there are a lot of messages on the bus, the messages with lower priority ID's may take longer to transmit because they will lose arbitration to other nodes with higher priority IDs.

The TX Buffer Add Request Transmission Occurred register (0x10D8) can be monitored to check when the message in the TX buffers has transmitted.  The TX Event FIFO can be used to create an event log for message transmission as well, but this takes additional MRAM space.

I also noticed you are using the TX Queue mode, and this will cause the device to check all the message IDs in the Queue to determine which message has the highest priority ID.  This can also lead to situations at high bus loading where lower priority messages are delayed which can appear to be "lost" while in fact they are still in the queue pending transmission.

You can find more detailed information about the RX and TX handling in the M_CAN User's Manual (Link).

Regards,

Jonathan