Tool/software:
Hello
Could you help us to know the maximum time expected to be consumed by below reset digital blocks 0 ?
Also what is the impact for the chronogramme shown in the "Figure 6. FPD-Link Outputs Enable Delay" ?
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Tool/software:
Hello
Could you help us to know the maximum time expected to be consumed by below reset digital blocks 0 ?
Also what is the impact for the chronogramme shown in the "Figure 6. FPD-Link Outputs Enable Delay" ?
Hey Nabil,
Toggling means OEN L->H or H->L or H->L->H or L->H->L. If this happens you need to issue digital reset after this as described in the datasheet.
Typically OEN enable delay is 6 ns but longer than the typical value listed in the datasheet may not actually cause any problems since the value is a typical value, not a maximum.
Regards,
Fadi A.
Hello Fadi
for the OEN activation letency of 6 ns is understood
Now the point is the for "reset by programming Register 0x01[0] for digital blocks" how additional delay will be consumed by this operation to have LVDS output operational again ?
Hey Nabil,
I will check and get back to you by Tuesday 11/19
Regards,
Fadi A.
Hey Nabil,
Depending on your I2C speed, display delay, video source delay, etc.
928 Lock will toggle within ~620 us when a digital reset is issued.
Display video will come back up within ~2 seconds total time on a typical bench setup with 927-928 using 927 internal patgen and a PC monitor.
Regards,
Fadi A.