• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 227 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TCAN4550-Q1: MISO always return 0x88000000 after CS and SCLK.

Xing Feng
Prodigy 10 points
Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Tool/software:

Linux platform TCAN4550 MISO alwasy retrun 0x88000000 after CS and SCLK for each SPI word operation(READ/WRITE/DATA).

SPI mode is zero, RESET pin was pull up then down by driver.

Anything we can check?

  • +1
    TI__Mastermind 33030 points

    Hi Xing,

    Can you capture waveforms of the SPI signals using a logic analzyer or scope?

    Since you mention that the RST pin is being toggled, there is a minimum 700us delay that must occur to let the device recover from the reset event before SPI activity can occur.  If you try SPI transactions within this 700us window of time following a reset event, they will fail.

    Common issues for SPI errors are that the SPI driver for the processor may be pulling the CS signal High after each word of data is transmitted instead of the complete SPI transaction.  Please verify the CS signal remains low for the entire SPI Read/Write transaction which is 64 bits for a single register read/write.  If the processor is breaking the SPI data into 8, 16, or 32 bit data chunks, then it is common to see the CS signal transition high after each chunk of data is transmitted and you will need to modify the SPI driver to hold CS low for the entire SPI read/write transaction.

    Other issues could be with the formatting of the SPI address data itself such as an incorrect value in the Length field that doesn't match the number of data words you are transmitting. 

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    Prodigy 10 points

    Thanks, Jonathan.

    We captured the SPI transfer and found that it will pull high CS for each word transfer. This should be the reason why we just get 0x88000000. 

    The Linux version is 4.14, there is no TCAN4550 driver in kernel, so we ported one old driver for newer kernel:

    commit bcc3d8ef14c044df225d9e2292ed3f1d5176c77d (HEAD)
    Author: Marc Kleine-Budde <mkl@pengutronix.de>
    Date: Wed Dec 16 00:17:32 2020 +0100
    can: tcan4x5x: beautify indention of tcan4x5x_of_match and tcan4x5x_id_table
    This patch beautifies the indention of the tcan4x5x_of_match and
    tcan4x5x_id_table.

     

    We are using DW MMIO SPI controller, not sure the linux 4.14 SPI controller driver is good or not.

    Do you have any suggestion which TCAN4550 and DW MMIO SPI driver we should use?

    Thanks

    Xing

  • +1 in reply to Xing Feng
    TI__Mastermind 33030 points

    Hi Xing,

    Yes, the CS signal transitioning high in the middle of the transaction is considered a SPI error and the device will ignore any SPI writes that contain errors.  Adjusting the driver to keep CS low for the complete transaction should resolve the SPI errors.

    Regarding your question about the DW MMIO SPI driver, I don't know.  My expertise is with the TCAN4550 device and not with Linux.  I can help with any questions related to the TCAN4550's register configuration, operation, and physical layer properties (i.e. hardware related) that you may have. 

    Regards,

    Jonathan