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TIC10024-Q1: MSDI start-up timing

Andreas Brugger
Prodigy 60 points

Part Number: TIC10024-Q1

Tool/software:

Hello Support team,

I'm looking for the start-up timing of the MSDI TIC10024-Q1.

Can you provide us numbers for the following start-up scenarios:

* Time from power-up (VS>=VPOR_R) until the device is initialized by default (resonator startup, self check, initialization).

* Time for re-initialization after a HW-reset or SW-reset

Best regards,

Andreas

  • 0
    TI__Mastermind 35590 points

    Hi Andreas,

    I can make some measurements on an EVM.  But I wanted to clarify that what you mean by "initialization" is simply the device setting the registers to the default value.  Is that correct?  The default value for the configurable registers is all zeros, so after the device has powered on or been reset, all of the registers will need to be re-configured through SPI, and that timing is controlled by the MCU.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    Prodigy 60 points

    Hi Jonathan,

    thanks a lot for your prompt reply.

    I'm referring to the datasheet chapter 8.3.3 Device initialization.

    For my understanding initialization at VS ramping up (VS>=VPOR_R) consists of: (assumption: clock is ramping up) + register initialization + state machine initialization + programming of factory settings + self check => INT_N assertion

    The SW reset described in chapter 8.3.5.3 says that the registers are reset to default (zero) values only -as you mentioned-.

    The initializaton after a HW reset is metioned to be similar to the POR initialization, so I guess it have similar timing.

    I need both timings, the one for POR init and SW reset init as shown in the scetch.

    Many thanks in advance for your support.
    Best regards,

    Andreas

  • 0 in reply to Andreas Brugger
    TI__Mastermind 35590 points

    Hi Andreas,

    Thanks for the clarification.  I can make a couple of measurements on an EVM and follow up with the measured values. 

    The device reset (either through hardware or software) is usually implemented by disabling the internal LDOs resulting in essentially a Power On Reset.  So I expect the timing to essentially be the same.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Mastermind 35590 points

    Hello Andreas,

    I made some measurements to give you some reference.  The datasheet footnote specifies up to 1ms for the device to complete a reset which would cover some additional delay that comes from different Process, Voltage, and Temperature combinations.

    For the power on timing, I took a measurement between the nINT falling from the both the VPOR_R min and max spec since the actual threshold is unknown but somewhere in this range.

    The delay time between VPOR_R = 3.85V to nINT was 625.75us.

    The delay time between VPOR_R = 4.5V to nINT was 574.25us.

    I took the Hardware reset from the 50% location on the falling edge of the Reset signal to nINT which was 727.32us.

    I took the Software reset from the rising edge of the SPI CS signal to the nINT which was 578.11us.

    Regards,

    Jonathan