Tool/software:
(1) I use dp83869 as a RGMII to SGMII Bridge to connect SOC and switch.
(2) I configured the following registers to make dp83869 work in bridge mode:
(3) After the configuration, when I power on the system, I found the switch SGMII and DP83869 SGMII can not link up each other.
Can you help to analyze the reason?
Thanks.
Hi Chenglei,
Thank you for providing the register values. You are correct, it look like the auto-negotiation process was not completed. Here are some things we can try
Auto-negotiation can be disabled through the register 0x14[7]. I am not sure if disabling and forcing a connection at a certain speed would work for bridge mode, but we can try doing it as a debug step. We can try disabling MDI auto-negotiation, and forcing a specific speed through register 0x00. Writing bit 12 to 0 would disable auto-negotiation on the MDI side, and bits 13 and 6 can be used to force a specific speed.
Best,
Vivaan
Hi Chenglei,
Thank you for all of this information. I am having some trouble understanding the register values.
0x01 power up default value is 0x6149
0x00 power up default value is 0x2100
You mentioned these registers are not initializing to the default values but the register dump you provided tells us that they are being initialized to 0x140 and 0x7949, not 0x2100 and 0x6149. Is this value being changed?
For the register value of 0x6E
Taking a look at the bits 11-9 above, it also looks like the auto-negotiation strap is set to disable, which is why bit 12 was 0 for you when you read it in register 0x00
Our bit12 of reg 0x00 is zero by power-up default, why?
This is for the MDI line auto-negotiation, which shouldn't matter when being used in bridge modes.
Can you also confirm that the extended register space access steps were followed while writing these registers to enable bridge mode? If possible, I'd like to read the register 0x1DF to make sure that the value 0x43.
Can we probe the SGMII signals (SO_P/SO_N & SI_P/SI_N) to make sure they are as expected? It should look similar to the following
Channel 1: SO_P
Channel 2: SO_N
Channel M1: CH1 - CH 2
Best,
Vivaan
Hi, Vivaan
Our hardware only pulled up RX_D3 to high, and leave RX_D2 and JTAG_TDO/GPIO_1 default low. Boot-up mode is RGMII to 100Base-FX.
After boot up, SGMII auto-nego was disabled. And I tried to enable it, but failed.
Can you help how to set registers to make auto-negotiation successful?
I found this from datasheet：
Our 83869 strp pin is in “RGMII to 100Base-FX” mode.
I wonder if we have ways to restart auto-nego when 83869 mode change from “RGMII to 100Base-FX” mode to "GRMII SGMII bridge" mode by software.
Hi Chenglei,
Thank you for the register dump and all the information
reg(0x 0) = 0x2100 " means auto-nego is disabled
I think you are confusing the MDI auto-negotiation with the SGMII auto-negotiation. The auto-negotiation referred to in the register 0x00 is the MDI auto-negotiation. Since in Bridge Mode, the MDI side is not used, this setting is not applicable at all. The SGMII auto-negotiation can be checked through register 0x14 bit 7, which according to the register dump you provided, is on.
Additionally, can you read register 0xC00 after writing the following registers ONLY (to put the PHY into Bridge Mode)?
I think this would confirm if the PHY is actually switching modes using that command since this register should change to reflect the new mode.
As mentioned in my earlier reply, it looks like the link partner is not responding to the auto-negotiation started by the PHY. TO get more information about this, I wanted to conduct the following test. This would tell us if there is an issue in the PHY signal or the link partner
Can we probe the SGMII signals (SO_P/SO_N & SI_P/SI_N) to make sure they are as expected? It should look similar to the following
Channel 1: SO_P
Channel 2: SO_N
Channel M1: CH1 - CH 2
We can probe these signals from bootup to after writing the register changes to change into bridge mode.
Best,
Vivaan
