DP83867CS: Compliance test Failed with DP83867C

Hi ttd,

Thank you for sharing the information. 

I would like some more detail for further debug:

• May I ask how long is the cable when you are performing the compliance test?
• If possible, could you check if you configure the following register correctly when you are performing compliance test:
  • 
• If possible, could you share the schematic around the MDI lines, transformer, and RJ45?

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Regards,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply.

●May I ask how long is the cable when you are performing the compliance test?　

　　　→Approx 20cm.

●If possible, could you check if you configure the following register correctly when you are performing compliance test

→There are no description about Reg 0x1D5 on datasheet. According to the rev history, it seems to remove from datasheet.

     Currently, 0xF508 is set for Reg 0x1D5.
　
    The Peak A vs Peak B that fails in the compliance result I gave you has a Current Value: -1.xx %,

    and I think it needs to be within the Test Criteria: -1.000 % < x < 1.000 % to pass,
     Should I adjust (increase?) the value from Reg 0x1D5=0xF508 ?
     If you suggest step for VoD with Reg 0x1D5 and what value is better to pass, could you share it?

●If possible, could you share the schematic around the MDI lines, transformer, and RJ45?

→I shared it through priave message.

Best Regards,

ttd

Hi ttd

I will take a look and provide you an response later today.

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Regards,

Hillman Lin

Hi ttd,

I discuss with the team internally. Could you try to decrease the register 0x00A3 and see if that could help with your current compliance result? We want to see what is the current status after you decrease the register 0x00A3 on the compliance.

If possible, we would like to confirm on your MDI lines impedance mismatch. Is there any mismatch between each pair of MDI lines?

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Thank you,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply.

>I discuss with the team internally. Could you try to decrease the register 0x00A3 and see if that could help with your current compliance result? We >want to see what is the current status after you decrease the register 0x00A3 on the compliance.

LD_FILTER_TUNE_D_FORCE_ CTRL and LD_FILTER_TUNE_C_FORCE_ CTRL should be enable and decrease LD_FILTER_TUNE_D and LD_FILTER_TUNE_C from 10000(default)? 0x00A2 are same register for AB.

This register adjust the Line driver swing level. When decreasing the register, does the swing level decrease and incresing the register goes the swing level increase?  

I will try this for failed channel.

>If possible, we would like to confirm on your MDI lines impedance mismatch. Is there any mismatch between each pair of MDI lines?

→Impedance control to 100Ω for differential signals between PHY chip and RJ45

    Could you tell me Where exactly does  “MDI traces must be 50 Ω to ground” needs to control?

　Is it correct that one of the MDI differentials is controlled by 50 Ω per wire and the differential is 100 Ω　layout?

I compared the 0826-1X1T-43-F with the TI datasheet,
I thought they were basically the same, albeit with an internal pulse transformer. Is this “0826-1X1T-43-F” appropriate?
Also, is there a list of recommended RJ45 connector model numbers?

dr-mag-0826-1x1t-43-f.pdf

Best Regards,

ttd

Hi ttd,

• If possible, could you let me know which register did you write when you try for 0x00A2 and 0x00A3 when you redo the compliance test?
• Yes, you are correct. MDI trace should be impedance match with 100ohms differentially.
• Integrated magnetic RJ45 connector do have worse performance compare to discrete magnetic and RJ45 design. The RJ45 shield may possibly weaken the magnetic isolation. 
• If possible could you only output single channel when you are preforming the compliance test and see which pair of wire provide the worse performance?

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Regards,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply.

You said:

• If possible, could you let me know which register did you write when you try for 0x00A2 and 0x00A3 when you redo the compliance test?

May I sent you the setting values for 0x00A2 [0:15] and 0x00A3 [0:15]? Do you need all the other register setting procedures that are set in DP83867?

Also, could you tell me how specifically setting LD_FILTER_TUNE_x_FORCE_CTRL for 0x00A2 and 0x00A3 changes the output swing level?
I'd like to avoid having a hard time confirming this with cut and try.

You said:

• If possible could you only output single channel when you are preforming the compliance test and see which pair of wire provide the worse performance?

Is it your intention that 3 of the 4 pairs (A,B,C,D) should be disabled and only 1 pair should be enabled and checked?
I think that the Fail in each Pair A,B,C,D item in the compliance test report I sent by internal message previously would be worse performance.

Please point out if my understanding is misunderstanding.

Best Regards,

ttd

Hi ttd,

If possible, we would like to see the difference on compliance test when you decrease the 0x00A2 and 0x00A3. We want to see if improvement are made.

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Regards,

Hillman Lin

Hi  Hillman Lin,

Thank you for you reply.

I have tried changing the values of 0xA2 and 0xA3 registers in various ways as follows.
However, Peak A vs Peak B test is still Fail.

<Tested settings>
0x2020  ⇒　LD_FILTER_TUNE_x= 0
0x2424  ⇒　LD_FILTER_TUNE_x= 100
0x2828  ⇒　LD_FILTER_TUNE_x= 1000
0x3030  ⇒　LD_FILTER_TUNE_x= 10000(default)
0x3434  ⇒　LD_FILTER_TUNE_x= 10100
0x3838  ⇒　LD_FILTER_TUNE_x= 11000

The amplitude strength of the signal can be strengthened or weakened by the above settings.
However, Peak A vs. Peak B is not within 1% of the specified value(Fail).

Incidentally, I tried changing the value of TXG_GAINSEL_FINE_X for 0xA0 and 0xA1.
This is also the same as before, but it is still Fail.

Best Regards,

ttd

Hi ttd,

I discuss with the team internally. Could you try the following configuration:

• 
• https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1367619/faq-dp83867e-1000base-t-ethernet-compliance-register-script

If possible, could you take a look on the layout checklist? Here are the mainly thing we would like to take a look at:

• MDI trace length, MDI impedance, MDI gaps between the differential pair
• 5305.Industrial_PHY_Layout Review Checklist.xlsx

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Regards,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply.

I will try your suggested configuration. 

I checked checklist before and following concern on MDI.

１．Length matching within 50 mils for 1G, 100 mils for 10/100M

The mismatch is within 50 mils for the MDI differential signal line, but TD_P_B/TD_M_B, TD_P_C/TD_M_C, and TD_P_D/TD_M_D exceed this.

２．Single differential pair should be routed as close together as possible (5-6 mils is prefer)

３．At least 30 mils to any other signal and 50 mils for other high speed signal spacing away from MDI channel

　　Make sure no unprotected traces or signal traces near MDI lines

TD_P_A/TD_M_A , TD_P_D/TD_M_D differential pair and GND plane may be close

Hi ttd,

I would wait for the update on the new configuration.

Regarding to the layout concern, may I ask what is the mismatch between TD_P_B/TD_M_B, TD_P_C/TD_M_C, and TD_P_D/TD_M_D?

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Thank you,

Hillman Lin

Hi ttd,

I am mainly looking for the length mismatch.

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Regards,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply.

In the differential signal routing, the difference in wiring length between P and N appeared to exceed the recommended value.

Length mismatch between TD_P_B/TD_M_B, TD_P_C/TD_M_C, and TD_P_D/TD_M_D 

Best Regards,

ttd

Hi ttd,

Thank you for sharing the update. I will wait for the result after you configure the register provided before.

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Regards,

Hillman Lin