DP83869HM: sampling of 100Base-FX / 1000Base-X / SGMII

viktor zalud

Part Number: DP83869HM

Tool/software:

Hello,

we have architecture where we must design such signal over several PCB and simulation shows that we have significant overshoot and undershoot. the maximal / minimal limit for input are not exceeding so it shall not be problem. But we would like to be sure and better understand how this PHY is working. So my question is how the reading of this signal is done. When you define that is logical "0" or "1". signal is sampled only one per half period or it is sampled multiple times. I exist some application note for this it would be great

9 months ago

0 Hillman Lin 9 months ago

TI__Mastermind 25945 points

Hi Victor,

There are a specification in the datasheet define VIL and VIH to show when will the signal sample as 1 or 0. Refer to table 6.5 in the datasheet for further information.

I am not fully follow your second questions. the sampling frequency depend on the interface that you are currently operate in.

Regards,

Hillman Lin

0 viktor zalud 9 months ago in reply to Hillman Lin

Prodigy 130 points

in the table 6,5 is mention only voltage limits or current. but there is no information when and how the sampling is done, It is done just one in the middle of period or it is done several times? In all communication principles there is always some exact time / times went the input IC check / sample the value and then decide that voltage level is 0 / 1. This is what I wanted to know in this PHY

0 Hillman Lin 9 months ago in reply to viktor zalud

TI__Mastermind 25945 points

Hi Victor,

I am not sure if I understand your concern correctly.

Depend on different MAC interface, there are some MAC interface sample only on the rising edge of the clock and some MAC interface sample both during rising and falling edge.

Regards,

Hillman Lin

0 viktor zalud 9 months ago in reply to Hillman Lin

Prodigy 130 points

ok, is there some way to make a call each other? Sure there is some clock recovery from the data.......how the clock recovery and sampling is done on this PHY

0 Hillman Lin 9 months ago in reply to viktor zalud

TI__Mastermind 25945 points

Hi Viktor,

May I ask which MAC interface are you trying to evaluate?

Regards,

Hillman Lin

0 viktor zalud 9 months ago in reply to Hillman Lin

Prodigy 130 points

currently the

100Base-FX / 1000Base-X

0 Hillman Lin 9 months ago in reply to viktor zalud

TI__Mastermind 25945 points

Hi victor,

SGMII operate in 625MHz frequency and sample on both rising and falling edge for both 100Mbps and 1000Mbps

100Base-FX and 1000Base-X frequency and sampling rate are also define in the standard.

Regards,

Hillman Lin

0 viktor zalud 9 months ago in reply to Hillman Lin

Prodigy 130 points

Hi Lin,

I am a ware that in 100Base-Fx / 1000Base-X is nothing about the sampling, at least I did not found it and this exactly reason why I raise those questions.

0 Hillman Lin 9 months ago in reply to viktor zalud

TI__Mastermind 25945 points

Hi Viktor,

Sorry, I am not still follow your concern completely. Maybe IEEE standard would be a good resource for you.

Sincerely,

Hillman Lin

Interface

Interface forum

DP83869HM: sampling of 100Base-FX / 1000Base-X / SGMII

100Base-FX / 1000Base-X