DS90UB954-Q1: DS90UB954-Q1 MIPI Retimer & Switch

Hello,

Due to US public holiday, support will be resumed on Monday Dec 2nd. Thank you for your patience.

Regards, 

Logan 

Hi Zoe

I'm use UB954 MIPI 4 lane out @800Mbps (954's 0x1F=2), ,does it work?

another question 

SNx5DPHY440SS lane port can be interchangeable for best layout possible?

(lane port swap or positive , negative trace swap)

Hi Larson,

I'm looping in an expert on SNx5DPHY440SS and will get back to you with feedback shortly.

Thanks,

Drew

Larson

MIPI DPHY1.2 is backward compatible with DPHY1.1.

Since this is a CSI-2 application, and CSI-2 does not have a back channel path, because of this, there is no requirement on lane ordering. Because there is no lane ordering requirement, there are more combinations which can be implemented. All possible combinations are supported by the DPHY440.

For all CSI-2 implementations, the polarity must be maintained between the CSI-2 Source and CSI-2 Sink. The DPHY440 does not support polarity inversion.

Please note DPHY440 lane 0 is a special lane. Please see this e2e FAQ for detailed explanation on lane 0. 

You can use TS3DV642-Q1 as a MIPI CSI-2 MUX.

Thanks

David

Hi David

attached PDF is the schematic 

Could you help to check is there any problem?

what I changed for layout:

1.DPHY440 :change the lane ordering 

2.TS3DV642-Q1 :change the lane ordering  and swap positive & negative signal 

thanks for help

8360.SCHEMATIC1 _ PAGE1.pdf