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Original question:

PROCESSOR-SDK-J784S4: XAUI and USXGMII related question on J784S4_TDA4AP TI processor.

DP83867IR: DP83867 Disable EEE / LPI

Annamalai Lakshmanan
Intellectual 330 points
Part Number: DP83867IR

Tool/software:

Dear TI

We have TI DP867 interfaced with dwceqos controller in a IMX8 Platform,

We see that when we unplug the cable when doing a spin loop in ifconfig we get spurious interrupt at MAC layer for EEE (Low power / Energy Efficiency)

Upon talking to the SOC Vendor, they mentioned this has to be disabled via PHY.

Upon looking into thread, I find following register writes can disable the EEE:

1) MMD register 0x31 bit 7 to be cleared

2) Register 1F, Enable bit 14 for SW Reset.

I tried above but still i keep getting LPI interrupts at the MAC Layer.

Please tell me if there are any further debug steps? and what can be done.

Or) If its not possible also please us know.

Regards

Annamalai

  • 0
    TI__Intellectual 2730 points

    Hi Annamalai,

    Thank you for your query

    The DP83867 does not support EEE, and therefore, cannot generate interrupts for EEE. More information about interrupts that are supported can be found in registers 0x12/0x13. The interrupts listed here are the ones that are toggled by the PHY, and these do not include an EEE interrupt. 

    Best,

    Vivaan

  • 0 in reply to Vivaan Jaiswal
    Intellectual 330 points

    HI Vivaan

    Thanks understood, we get a EEE interrupt from MAC and not this PHY. The MAC vendor suggested that we need disable EEE from this PHY.

    So that the MAC dont generate this interrupt.

    What are your thoughts on this.

    Regards,

    Annamalai

  • 0 in reply to Annamalai Lakshmanan
    TI__Intellectual 2730 points

    Hi Annamalai, 

    Since EEE is not supported by the PHY, it cannot be enabled or disabled. The default state of EEE, if it is supported, is disabled anyhow. I don't believe the interrupt is caused due to PHY settings. Kindly consult the MAC vendor for this interrupt. 

    Best,

    Vivaan