Other Parts Discussed in Thread: DS100DF410, DS125DF410, DS125DF410EVM
Tool/software:
Refer:www.ti.com/.../snlu126c.pdf f_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252Fja-jp%252FD
① Could you provide a searchable schematic ""pdf"" for 6.Schematic, as the current schematic captures attached do not allow for signal name searches?(Purpose: Unable to search for signal names due to schematic capture attachments.)
② Regarding the loop filter connection between LPF_REF_x and LPF_CP_1, the evaluation board uses jumper leads (Loc.J28, J29, J30, J31). What is the purpose of this? Is it unnecessary during design?
③ Regarding REFCLK, we understand that the evaluation board allows oscillator EN control via a debugger header.But for DS110DF410, there is no sequence requirement between VDD and REFCLK. Connecting VDD=2.5V directly/simultaneously with the oscillator EN (REFCLK output) is acceptable. Is this understanding correct?
④ The LDO (LP3874EMP-2.5) circuit allows EN control via a debugger header. Is it acceptable to connect Vin directly to SD_N ?(similar to question ③)
