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DP83867IR: PHY Strap and Communication Issues

Shyam Daram
Expert 1275 points
Part Number: DP83867IR

Tool/software:

Setup:

  • Using DP83867 PHY in RGMII mode.
  • Observing differences between a working board and a non-working board.
  • Focus is on strap pins (e.g., RX_D0, RX_D2, RX_CTRL) and MDIO/MDC communication

Schematic:

Power-Up Observations:

  • Working Board:
    • RX_D0 is consistently low during power-up and reset.
    • RX_D2 is consistently low during power-up, matching expected behavior.
    • PHY communicates over MDIO/MDC, and MDIO/MDC toggling is observed.
  • Non-Working Board:
    • RX_D0 is high, even though it is pulled low in the schematic.
    • RX_D2 is also low, matching the working board.
    • MDIO/MDC do not toggle, and PHY is unresponsive to MPSOC commands.

Connection to PC PHY:

  • Despite these issues, the PHY on the non-working board successfully establishes a 100 Mbps link with a PC.
  • RX activity is observed via LEDs, indicating basic link functionality.

Request for Assistance:

  • Does the power sequencing of VDDIO relative to VDDA and VDD1P1 directly affect strap pin behavior?
  • Could slow ramping of VDDIO cause the PHY to incorrectly latch RX_D0 as high?
  • Are there other possible causes for RX_D0 being high despite a pull-down resistor in the schematic?
  • 0
    TI__Mastermind 25955 points

    Hi Daram,

    Power up sequence of the PHY do have an effect on the strap stage.

    May I ask what is the VDDIO ramp up timing?

    We would also like to check if SoC is sending any signal to the PHY during power up?

    --

    Regards,

    Hillman Lin

  • 0
    TI__Mastermind 25955 points

    Hi Daram,

    Power up sequence of the PHY do have an effect on the strap stage.

    May I ask what is the VDDIO ramp up timing?

    We would also like to check if SoC is sending any signal to the PHY during power up?

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Expert 1275 points

    I will get back with ramp times of all rails after POR from MPSOC(XIlinx PL+PS device), its the PMIC which generates POR to DP83867 after the power rails stabilize, PMIC is TI TPS6508641

    I have also tried differently by using Reset button to reset post powerup, all these experiments are happening without programming FPGA,/ PS side of FPGA

    so there is no chance that MPSOC will try to send some signals of data 

    can you please explain in what situation the strap pin D0 state would become like this, its not that phy is hanged or faulty its able to connect to PC for reception by FPGA to PHY link is not happening

  • 0 in reply to Shyam Daram
    Expert 1275 points

    Non Working Board

    WWorking Board

    II dont much see any big difference or deviation, so i dont feel its the supply issue also

    i did a mistake and misunderstood that rxd0 is high post power on, but actually once the phy is connected to pc this status happens, so while testing the non working board i was plugging in the eth jack, the same i repeated with working board both behaved same

    coming back to the observaton, mainly the MDC and MDIO toggling doesnt happen between MPSOC and PHY which is were i am stuck, why this happens ? in what situiation, how to see through hardware pins if PHY is non functional ?

    I checked clk out and its perfect, now as per new observation, strap pins are also fine, ramp up of voltages is also fine, what else might be contributing to this unknown behavior ?

  • 0 in reply to Shyam Daram
    TI__Mastermind 25955 points

    Hi Shyam,

    Mau I ask what does yellow, blue, and green trace represent in your plot?

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Expert 1275 points

    You can just co-relate from V/div and the voltage read, there are just three rails 2.5v, 1.1v, 1.8v

    now on working board, 2.5v took 6mS to rampup 1.8v took less than 1mS to ramp up 1.1v took late by 1mS from other startup but ramped very quickly POR almost 55mS to ramp up

    my observation on non-working board, all voltages started to ramp at same time except 1.1v, only 1.1v started after 1mS, 2.5v to build to full voltage took 6mS and 1.8v ramped up in 1mS and 1.1v even though started late by 1mS but ramped up very quickly
    so i dont see any big difference 
    post removal of RJ45 during test, as said strap pins also behaving same
    now the setup is two boards are powered on and both are flashed, on one MDIO MDC toggling happens after code flash and doesnt happen on non-working board
    i checked layout, i checked pin planning everything looks fine, something else might be affecting in what situation MDIO and MDC can be stuck ?
    clock out of PHY is proper, connection with PC for Reception is fine, LEDs are glowing and blinking as expected.
    I need to find a way forward from here, kindly provide your valuable guidance
  • 0 in reply to Shyam Daram
    TI__Mastermind 25955 points

    Hi Daram,

    Thank you for the update.

    When there are MDIO/MDC signal when PHY is power up. There will be a possibility that MDC clock signal has interference with the reference clock signal inside the PHY which bring the PHY into un-known stage. Making sure there are no MDC/MDIO toggling when the PHY is powering up is important.

    After the PHY is in "unknown stage" where RX_D0 strapping is incorrect and MDIO/MDC is not toggling, could you try a hardware reset to see if the PHY is able to recover after that?

    If you also pull the RX_D0 low and perform the hardware reset, could you bring the PHY out of "unknown stage"

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Expert 1275 points

    What i did is below

    1. Case 1 : populated a reset button and did hardware reset of PHY through the button to see if it comes out of some expected locked state, it did not happen

    2. Case 2 : tapped the MDIO and MDC pins during powerup, post powerup and post code flash in none of the cases the MDIO and MDC did not show any change/toggle

    Regarding RX_DO as i said it my mistake of testing, the RX_DO state is same in both boards during and post power up, so its not an issue.

  • 0 in reply to Shyam Daram
    TI__Mastermind 25955 points

    Hi Daram,

    Sorry Daram, I would like to ask some more questions to confirm on the "stuck stage".

    If possible, could you help me to clarify on the observation during the "stuck stage"?

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Expert 1275 points

    my only doubt is why the MDIO and MDC pins are not toggling, i am suspecting from code also, let me comeback after confirming that there is no problem with code.

  • 0 in reply to Shyam Daram
    TI__Mastermind 25955 points

    Hi Daram,

    Thank you for the update. I will wait for your feedback.

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Expert 1275 points

    Thanks for your time and efforts in helping me

    I blindly trusted the software tool chain, there was a issue with software configuration, because of this the code was not loading to DRAM and there by not runnning on PS side, so hence the eth core on PS side was not initiating any communication to PHY

    A clear situation of software bug

  • 0 in reply to Shyam Daram
    TI__Mastermind 25955 points

    Hi Daram,

    Glad that you are able to solve the issue. Thank you for the update.

    --

    Regards,

    Hillman Lin