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TMUXHS4412: PCIE4.0 AC couple cap place

Tonyx.wu
Genius 3215 points
Part Number: TMUXHS4412

Tool/software:

on spec of TMUXHS4412, I found 3 AC couple cap placement option as Figure7-1

in my board, no connector, all devices are on the same board, and the endpoint is very close to TMUXHS4412.

To save the space and minus the cap qty, i want to change place of the endpoint ac couple cap as attached pic.   From Endpoint TX side to TMUXHS4412 TX side. Pls confirm if it is OK.

2nd question.

The TMUXHS4412 can tolerate polarity inversions for all differential signals on Ports D, DA, and DB. In such flexible implementation, users must ensure that the same polarity is maintained on Port D versus Ports DA/DB.

if the PCIE host and endpoint support polarity inversions. 

Below strucure should be OK, pls help to confirm, thanks.

  • 0
    Prodigy 90 points

    3rd question

    Is there any HFSS model available for us to do the fanout optimization?

    4th question

    Could you recommend the void size of DA/DB/D pin pads?

    Thanks!

  • 0 in reply to QIANWEN WANG
    TI__Mastermind 18711 points

    Hello,

    1. I believe your suggested AC coupling capacitor placement would follow Figure 7-1 (b). Please correct me if I've not understood the proposed placement correctly.
    2. Based on the data sheet definition, if P or N are swapped at either the D side or DA/DB side, the other side must follow. I do not believe all of the proposed connections follow this rule. Please see this other E2E post for a similar inquiry.
    3. There should be an S-parameter model available for this part. Let me check with a colleague on this.
    4. Please see this application note for TI's recommended layout guidelines with this device: https://www.ti.com/lit/an/slaae45/slaae45.pdf

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 90 points

    Hi David,

    Thanks for your reply.

    1.We proposed to put the cap between Host RX and MUX TX instead of between EndPoint Tx and MUX Rx on the upstream link. This can help to reduce the cap number so as to save the routing space.

    2.Does that mean only if the polarity of D side and DA/DB side can keep the same, it will have no issue with the link?

    3. I've downloaded the S-parameter model from the website. But for a 3D simulation, a 3D HFSS model will be the best choice. Could you help to double check with it?

    4.This guide only shows the void design under ESD/EMI component. What we'd like to know is the void size under mux pin pad

  • 0 in reply to QIANWEN WANG
    Prodigy 90 points

    BTW, for question2, could you please help to confirm if the below three connections are all feasible? 

  • 0 in reply to David Waier
    Prodigy 110 points

    David

        This is Fupeng from the same team with Qianwen. And this case belongs to our new PCIe design. We are using TMUXHS4412 to deal with a PCIe add in card. The card is using on data center server. so that we can not make sure the PN polarity from host server, since it belongs to another dedicated system. 

        So, I mean, can you confirm when TMUXHS4412 is working on PCIe application , even the PCIe device all support exchanged PN polarity, should commit the same PN inversions in the whole system design? 

  • 0 in reply to wang fupeng
    TI__Mastermind 18711 points

    Hello Qianwen, Fupeng,

    QIANWEN WANG said:

    1.We proposed to put the cap between Host RX and MUX TX instead of between EndPoint Tx and MUX Rx on the upstream link. This can help to reduce the cap number so as to save the routing space.

    • Thank you for clarifying the proposed location of AC coupling capacitors in your design. Based on your comments regarding the system's topology (data center server), I would like to point out a couple of items.
      1. The AC coupling capacitor recommendation for this device is due to the common-mode voltage (CMV) requirement of the device. Please see data sheet section 7-1 for this detail
      2. If the system board is being used with multiple endpoints, some which may not fall into the TMUXHS4412's CMV range, then AC coupling capacitors would be needed on the RX side of the DA/DB pins of the TMUXHS4412. The caps could not be moved to the TX side of the D pins of the device.
      3. An FAQ regarding this question can be found here.
    QIANWEN WANG said:
    2.Does that mean only if the polarity of D side and DA/DB side can keep the same, it will have no issue with the link?
    QIANWEN WANG said:

    BTW, for question2, could you please help to confirm if the below three connections are all feasible? 

    • I have checked with a colleague on this item. These polarity swaps are OK, as the polarity check should be done by the PCIe RC and EP in the system. The MUX should not care about the polarity.
    QIANWEN WANG said:
    3. I've downloaded the S-parameter model from the website. But for a 3D simulation, a 3D HFSS model will be the best choice. Could you help to double check with it?
    • Unfortunately, we do not have an HFSS model for this device.
    QIANWEN WANG said:
    4.This guide only shows the void design under ESD/EMI component. What we'd like to know is the void size under mux pin pad
    • The void in the plane below the TMUXHS4412 high speed pins should be the size of the pad for the device.

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 90 points

    Thanks David! 

  • 0 in reply to David Waier
    Prodigy 90 points

    Hi David,

    Several more questions about Q4.

    1.Which kind of the void shape do you recommend?

    A: individual void under each pin pad or B :combined void for differential pin pad

    2. For the void design you recommended, what's the target impedance of your optimization?

    3. What's the pcb material type as well as the height between top layer and the pin pad's reference layer after voiding? 

  • 0 in reply to QIANWEN WANG
    TI__Mastermind 18711 points

    Hi Qianwen,

    1. Either shape could be used. I believe this reference EVM uses shape B.
    2. Typical target differential impedance is 85 Ohms for add-in cards. System motherboards may target 100 Ohm differential impedance, so care should be taken.
    3. Megtron 6 is a typical material used for high speed applications, though I would say that the decision should be made based on simulation results. I do not have a specific recommendation for height of the top layer vs. reference layer.

    For most of these topics, I would recommend to perform PCB simulations to better understand your PCB's layout.

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 90 points

    Hi David，

    Let me explain why I have these questions.

    We attempted to get a HFSS 3D model to do the fanout impedance optimization based on our designed board. 

    Unfortunately, the model is no available. Besides, we have no idea what is the pin connection structure inside the mux either. So it's hard for us to set up the proper excitation port for the simulation.

    Thus, we'd like to follow your reference design. The height between the top layer and the reference layer after voiding, the void size as well as the PCB material are all influence factors. We want to clarify if the reference void design could be applied in our design deirectly.

    If it is convenient, could you share the method of how to set up the excitation port on pad without mux 3D model?

  • 0 in reply to QIANWEN WANG
    TI__Mastermind 18711 points

    Hi Qianwen,

    Thank you for explaining the origin of your questions.

    Please allow us to share these files with you via E2E private message. I am thinking that this may help to answer some of your questions about the layout with this device.

    Best,
    David

  • 0 in reply to David Waier
    Prodigy 90 points

    Thanks David ! Is there any extra action that I need to take for receiving these files? or Just wait for your share link?

  • 0 in reply to QIANWEN WANG
    TI__Mastermind 25470 points

    Hi Qianwen,

    Sorry for the delay on this, please accept my E2E Friend request and I can send over the EVM design files for you to reference for designing your system.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    Prodigy 90 points

    Hi Ryan,

    I've accepted the request. I think it should be ready for receiving your files now.

  • 0
    Prodigy 110 points

    Hi David

        I'd like to invite you to review our TMUXHS4412 design in case any missing point. thanks. 

  • 0 in reply to wang fupeng
    TI__Mastermind 25470 points

    Hi Wang and Qianwen,

    I sent out those design files to you over PM Qianwen.

    Wang, I don't see any major issues with this design. However, I would like to double check, are there .22uF caps on the PCIE lines? These are required.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    Prodigy 110 points

    yeah, the caps are used. And we finally put the cap between MUX and our EP TX. pls also see below topology

  • 0 in reply to wang fupeng
    TI__Mastermind 25470 points

    Hi Wang,

    Got it. In that case, I don't have any more input, seems good to me.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    Prodigy 110 points

    Ryan

        Sorry for missing. I must point out that the PCIe endpoint in my diagram use a zero-voltage common mode design. that means the Rx has its termination to ground. Means 0v Vcm for PCIe MUX which connect to PCIe endpoint directly. is it ok for MUX? thanks. 

  • 0 in reply to wang fupeng
    Prodigy 110 points

    add updated diagram

  • 0 in reply to wang fupeng
    TI__Mastermind 25470 points

    Hi Wang,

    As long as the Vcm is 0V and does not have any extensive negative signaling, this should be okay. The TMUXHS4412 supports different Vcm's based on VCC, though 0V is supported regardless.

    Also, to double check, does the PCIe Root complex also have a Vcm of 0V? Ideally, the entire system should have 0V Vcm, just to have everything match.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    Prodigy 110 points

    Ryan

    Sorry for late, actually I can not commit the Vcm of RC is 0v. it not depends. Since the MUX connected to RC directly and the MUX connected to EP belong to different chip. should they use the same Vcm? I mean maybe the RC has its own Vcm, not 0. 

  • 0 in reply to wang fupeng
    TI__Mastermind 25470 points

    Hi Wang,

    Ideally, both sides of the mux have the same Vcm. Do you know what the Vcm of the RC is? It needs to stay within the range acceptable by the mux:

    If needed, I believe the Vcm can be biased down to 0V to keep it consistent.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    Prodigy 110 points

    Ryan

        Our PCB belongs to PCIe add in card. we can not commit the Vcm of different RC. this is also the risk we already know and take. thanks for your support.  

  • 0 in reply to wang fupeng
    TI__Mastermind 25470 points

    Hi Wang,

    Understood. Again, as long as the Vcm in within the muxes acceptable range, it should be fine for the mux.

    Please let me know if there are any other questions.

    Thanks,

    Ryan