DP83867IS: About IDLE ERROR COUNTER in register 0x000A bit[7:0].

Hi Atsushi-san,

IDLE Error would happen when the signal quality degrade, the IPG is not matching the standard, or there are FIFO in the system.

If possible, could I ask for the register dump from 0x0000 to 0x001F?

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Regards,

Hillman Lin

Hi Hillman-san,

Thank you for your reply.

I'll send you the register information by private massage.

Hi Atsushi-san,

Thank you for sharing the information.

One thing I would like to confirm with you. May I ask which MAC interface are you using?

If you are using RGMII MAC interface, did you have RGMII shift mode enable in your application? We are thinking it might be FIFO causing the maximum IDLE errors. Adding a delay between data and clock.

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Regards,

Hillman Lin

Hi Hillman-san,

Thank you for your reply.

They are using SGMII.

Please let us know if you have any concerns about the register I sent you.

Hi Atsushi-san,

Thank you for your info. Here are some test we would like you help on:

• Perform a reverse loopback on the PHY, and send signals on the link partner side. Read back the signal on the link partner side and see if IDLE error still exist. This could rule out if the issue is on the MDI lines. 
• When there are maximum IDLE errors, it might be the FIFO or the clock frequency different between the processor and the PHY. One thing I would check is the average clock frequency between the processor clock signal and PHY's clock signal.

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Regards,

Hillman Lin

Hi Hillman-san,

Thank you for your reply.

I'll try your advice.

I have a question.

How does the device behave when IDLE ERROR COUNTER reaches the upper limit? Does it continue to operate? Does it stop operating?

The customer would like to know this.

This is one question when I created this thread.

Hi Atsushi-san,

There might be a potential packets loss and packets errors when IDLE Error counter reaches maximum.

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Regards,

Hillman Lin

Hi Hillman-san,

Thank you for your reply.

You said the following in the previous post.

Could you tell me more detail about this?

”When there are maximum IDLE errors, it might be the FIFO or the clock frequency different between the processor and the PHY. One thing I would check is the average clock frequency between the processor clock signal and PHY's clock signal."

1) What does FIFO mean here? Pease tell me specific example of FIFO.

2) What does "the clock frequency between the processor and the PHY" mean here at SGMII? SGMII_CON/COP or XI?

Hi Atsushi-san,

I will get back to you later this week.

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Regards,

Hillman Lin

Hi Atusushi-san,

The FIFO means the packets send from the link partner to the packets going to send on the SoC side.

Hopefully, the following E2E could help you explain the FIFO scenario:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1099943/faq-how-to-select-the-crystal-s-ppm-specification-for-an-ethernet-system?tisearch=e2e-sitesearch&keymatch=RMII%2525252520clock#

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Regards,

Hillman Lin