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Original question:

[FAQ] SN65DSI84: No display output with SN65DSI83, SN65DSI84, SN65DSI85

SN65DSI83: SN65DSI83 - LVDS bridge does not transmit received date of DSI-Lanes

Isaac Lucas de Lima Yuki
Intellectual 315 points
Part Number: SN65DSI83


Tool/software:

Hello,

I'm working on a problem which could not have been resolved: The LVDS bridge does not transmit data.

I can see DSI Data and CLK on the DSI side, the power up is done after the datasheet, the clock is beeing transmited on the LVDS-side, but I can not see any data beeing transmited on the LVDS-side.

I'm using a Tianma display (TM070JVHG33) which works between 62 - 78 MHz. 

The Testpattern on the SN65DSI83 bridge which is set with I2C works. We do not have a reference clock, the bridge is working with the DSI-Lane-CLK.  The Timing parameters as well the Clocks were set using the "DSI tuner"-tool from TI.

My configurations are:

```

// TIMING - Was checked with Display parameters

#define DEMO_HSW 1  
#define DEMO_HFP 64 
#define DEMO_HBP 5  
#define DEMO_VSW 1  
#define DEMO_VFP 40 
#define DEMO_VBP 2  
//DSI Polarity flags:
#define DEMO_LCDIF_POL_FLAGS                                                   \
  (kLCDIFV2_DataEnableActiveHigh | kLCDIFV2_VsyncActiveLow                     \
   | kLCDIFV2_HsyncActiveLow | kLCDIFV2_DriveDataOnFallingClkEdge)
//DSI CONFIG
```
  const dsi_dpi_config_t dpiConfig = {.pixelPayloadSize = DEMO_PANEL_WIDTH,
                                      .dpiColorCoding   = kDSI_Dpi24Bit,
                                      .pixelPacket      = kDSI_PixelPacket24Bit,
                                      .videoMode        = kDSI_DpiNonBurstWithSyncEvent, //  burst mode was tried as well
                                      .bllpMode         = kDSI_DpiBllpLowPower,
                                      .polarityFlags    = kDSI_DpiVsyncActiveLow
                                                       | kDSI_DpiHsyncActiveLow,
                                      .hfp            = DEMO_HFP,
                                      .hbp            = DEMO_HBP,
                                      .hsw            = DEMO_HSW,
                                      .vfp            = DEMO_VFP,
                                      .vbp            = DEMO_VBP,
                                      .panelHeight    = DEMO_PANEL_HEIGHT,
                                      .virtualChannel = 0};
```
//LVDS BRIDGE SETTINGS:
  SN65DSI83_WriteCSR(0x0Au, 0x05u);  //We're operating the LVDS on 66MHZ
  SN65DSI83_WriteCSR(0x0Bu, 0b00101000); // div= 6  -> LVDS CLK
  SN65DSI83_WriteCSR(0x10u, 0b00110000); // 2 lanes -> We're working from 2 DSI LANES
  SN65DSI83_WriteCSR(0x12u, 79u); //We're operating the DSI-CLK on 396 MHz without reference clk
  SN65DSI83_WriteCSR(0x18u, 0x7Au);  // Format1(24 bpp to 24 bpp, VS_Pol=Negative, HS_POL= Neg, Data-Enable=positive)
```

I already tested everything to make sure the power up meets the timing requirements like in here:

blue: DSI-lane, red: enable Pin, yellow: Clock-Lane fs= 1GHz..

blue: DSI-lane, red: enable Pin, yellow: Clock-Lane fs= 1GHz.. (blue is 500mV/div, so its max is 1.3V)

 

In this picture we can see, that the clock is transmited and is set right:

Could someone give any advice on this issue? What am I doing wrong?

Thank you for your help!

Isaac