DS110DF111: Retimer not detecting signal and CDR not locking

Hi Jack,

I reviewed your .cfg file and it appears to match default configuration. Polarity is not inverted in register 0x1F.

The retimer does not detect any signal at the receivers of both channels. This can be checked in register 0x54 bit 7.

Have you confirmed that a valid signal is being transmitted to the retimer? What is the amplitude of this signal?

Do you have multiple boards of this design? Do all boards experience this issue, or only one unit?

Best,

Lucas

Hi Lucas, thanks for the review. 

Here are some comments to your question:

I should have been more clear about my Output Data Polarity statement above - my apologies for any confusion. I meant to say was that the only change (register write) I had to make when powering up the retimer was to invert the OUTA and OUTB signals because the board design has these swapped to facilitate routing. I see value of 55 for register 0x1F for both CHA and CHB which I believe is incorrect for inverting the polarity, and should be 0x1F=0xD5. All other registers were left at default values.

Yes, a valid signal is being transmitted, with signal levels complaint to IEEE 802.3. The processor provides two 10GBASE-KR interfaces. As such, this custom board features two DS110DF111 retimers and the other retimer is functioning properly (signal is detected, CDR locks, can communicate at 10G via SFP+ to optical switch).

Yes, there are multiple boards for this design and all have been tested. On the passing boards, both retimers (on each board) are operating as intended. It's just this particular board that had both retimers working initially and now upon burn-in re-testing of the 10G interfaces, one of the retimers appears to be non-function, or even defective. 

Are there any registers that I should be experimenting with for troubleshooting? Also, would a poor REFCLK interfere with the retimer such that it would not detect an input signal even if it's valid?

Hi Jack,

Thank you for the clarifications. One more thing I want to check, are 10G-KR protocols such as auto-negotiation and link training enabled?

If only one link isn't coming up correctly, this does suggest that the retimer or another component may be non-functional.

Just to confirm, was the register configuration that you share with me captured while the retimer should be operational? Since register 0x54[7]=0 on both channels, this means the retimer does not detect a signal and explains why the retimer isn't achieving CDR lock or unmuting the output. Since all register values match default configuration, there aren't any further details that can be extracted from the registers.

It is possible that a poor REFCLK could affect retimer behavior. Can you check the following items to ensure there aren't any issues with the retimer's inputs?

• Confirm REFCLK_IN input signal meets datasheet specs
• Confirm power supply is stable
• Confirm TX_DIS pin is pulled low
• Confirm all external components are populated as expected

Another good test to perform is ABA swap. If you swap the suspect chip with another DS110DF111 chip on a known working board, you can check if the issue follows the chip or follows the board. However I suggest checking the above list first because ABA swap is more involved.

Additionally, can you share the schematic? I can review and check if I have any concerns with the design.

Best,

Lucas