SN65MLVD040: How does the failsafe feature work?

Lauren Mayfield

Part Number: SN65MLVD040

Tool/software:

Can you describe what is meant by "Type-2 receivers implement a failsafe by using an offset threshold. The xFSEN pins is used to select the Type-1 and Type-2 receiver for each of the channels", from the datasheet?

What is the offset threshold and how is this a failsafe method?

Thanks,
Lauren

9 months ago

0 Clemens Ladisch 9 months ago

Guru 317320 points

For type-1 receivers, a differential input voltage of 0 V is invalid.
For type-2 receivers, a differential input voltage of 0 V results in a low output.

See the Introduction to M-LVDS (TIA/EIA-899) Application Report.

+1 Eric Hackett 9 months ago in reply to Clemens Ladisch

TI__Guru 74292 points

Clemens,

Thanks for the help!

Lauren,

Please let us know if you have any other questions.

Regards,

Eric Hackett

0 Lauren Mayfield 9 months ago in reply to Eric Hackett

TI__Expert 7925 points

Hey Eric,

Thanks for the response and app note. Follow-up question, does the receiver's output oscillate when VID is between 65mV and 135mV? The datasheet shows that the output is unknown, but my customer wants to ensure it doesn't oscillate.

Thanks,
Lauren

+1 Clemens Ladisch 9 months ago in reply to Lauren Mayfield

Guru 317320 points

Type-1 receivers have 25 mV of hysteresis, so they will not oscillate if there is no noise on the inputs.

Type-2 receivers have no hysteresis. The differential input voltage is required to go through the region between 65 mV and 135 mV very fast; otherwise, it might oscillate. (This is usually not a problem for normal (M)LVDS outputs.)

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SN65MLVD040: How does the failsafe feature work?