Tool/software:
Dears,
We are using TLK1501 to transmit data in between two FPGAs. In the FPGA side we wait for at least 0.4 ms for pll setup, receive idles and than transmit counter values counting up. In the receiving side we see errors.
Is it expected? We want no loss in the transmission.
ENABLE='1'
LCKREFN='1'
PRBSEN='0'
TX_ER='0'
TX_EN ='1' when transmitting data.
We capture errors by ila triggered with RX_ER='1'
There were no errors when LOOPEN is 1. When LOOPEN is 0 and there is external loopback in one side we see errors and word loss.
Here is the link showing some captures from ila.
Thank you for your attention,