• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 307 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83869HM: The technology issue for DP83869HM

Zhang Liang
Genius 4235 points
Part Number: DP83869HM


Tool/software:

Hi,

We use the DP83869HM for our 1000M Ethernet PHY, and now, the Ethernet transfer data will disconnect for stress testing in 10min sometimes,

Plesae refer to below image, the max. data package is only 4M, and the Auto Negotiation ( 1000 Advertised) is fine, 

 

The schematic diagram please refer to below PDF:

3566.1000BASE_T PHY_updata.pdf

  • 0
    TI__Mastermind 40275 points

    Hello,

    I would imagine that there are significant signal integrity issues or PHY setup issues that are contributing to this reported behavior. 

    As next step, I would advise consulting against our DP83869 troubleshooting guide to rule out the common issues. If the document is not able to resolve your issue, we can take up further on this thread.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Genius 4235 points

    Hi Gerome,

    We use the FPGA for the processor, and now, we use two same design and Software boards for PING, one of the boards for data transfer speed well,

    but the other one is very slowly, please refer to below video and provide your comment that how to solve this issue?( We can get the waveform, 

    eye pattern and so on)

    Normal:

    Abnormal:

  • 0 in reply to Zhang Liang
    TI__Mastermind 40275 points

    Hello,

    Please refer to SNLA443. I would suggest isolating whether or not the MAC interface is the issue vs the MDI. Please consult section 2.5 for this.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Genius 4235 points

    Hi Gerome,

    Gerome Cacho said:
    I would suggest isolating whether or not the MAC interface is the issue vs the MDI.

    Sorry for our lack of experience, can you help to provide the detail test process that we can get the result, and Based on your experience, 

    need we to discuss this issue together with FPGA software engineer? thanks.

  • 0 in reply to Zhang Liang
    TI__Mastermind 40275 points

    Hello,

    Please consult section 2.5 of SNLA443 for test process. The idea would be to program loopback on PHY (Reverse loopback to test MDI, or MII loopback to test MAC) and have a packet generator send traffic accordingly, and receive the same traffic back. 

    Sincerely,

    Gerome