Tool/software:
Hi,
I need to design bridge from 3.3V DSI levels to LVDS. SN65DSI83 does not toleate 3.3V logic levels.
There are some level translator buffer chips in market, but they are more expensive than SN65DSI83 itself.
I was thinkng to use something like SN74AUC2G34, but its speed limited 350 MHz. DSI speed can reach 1Gbps.
Regards,
Mike
Hi Mike,
Is this a compliant MIPI DSI signal?
The following screen captures are from the MIPI DPHY CTS and Specification.
For a differential data pair the compliant swing is as follows:
For the LP transmitter the voltages are as follows:
For the LP TX of the clock:
Unfortunately we do not have any defined solution for this problem. Its probably best to use a high bandwidth level shifter even if it is expensive to make sure you are able to properly leverage the DSI83.
