Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 60 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

TFP401: Connect the TFP401 with two SN65LVDS93

Axel Chaudron
Prodigy 10 points
Part Number: TFP401
Other Parts Discussed in Thread: SN65LVDS93B, DS90C387A,

Tool/software:

Hi everyone,

I have an issue I’d like to clarify. Due to the temperature constraints (my requirement is that the components must operate between -40°C and 80°C), I cannot follow the SALL325 document that explains how to bridge DVI to LVDS for a higher resolution (1920x1200).

Instead, my idea is to use two SN65LVDS93B chips rather than a single DS90C387A. My question is: would this approach work?

Here’s my reasoning:

  1. I would connect the even pixels from the TFP401 to the first SN65LVDS93B.
  2. I would connect the odd pixels from the TFP401 to the second SN65LVDS93B.
  3. Both SN65LVDS93B chips would share the same ODCK, HSYNC, VSYNC, and DE signals.

Could anyone confirm if this setup is viable?

Thank you in advance for your help!

Best regards,

  • 0
    TI__Mastermind 22925 points

    Hi Axel,

    the questions regarding the SN65LVDS93B are more suited for the FPD-link team. I will assign this thread to then so you can get the proper expertise required.

    The TFP401 will work in this application. 

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 10585 points

    Hi Axel,

    My only concern here is if the TFP401 will be outputting the even and odd pixels simultaneously through PIXS (2-pixel/clock).

    The TFP401 can output even and odd pixels on separate E/O Q pins, ensure that this is also clocked out at the same rate that the SN65LVDS93B chips will be using for CLK input.

    The approximate PCLK appears to be 152.064 MHz for 1920 x 1200 pixels @ 60fps, with 10% blanking. It appears this may be outside the 85 MHz max for the LVDS93B devices.

    Would your approach be different here, such as using 1-pixel/clock on even/odd output and using half of the TFP401 CLK for each SN65LVDS93B device?

    Please let me know your thoughts on this.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 10 points

    Hi Miguel,

    I agree this is an important detail to consider.

    Since the TFP401 can output even and odd pixels simultaneously through its QE and QO channels in 2-pixel/clock mode, don’t you think that will work with a Dual Channel LVDS configuration (using two SN65LVDS93B devices)?

    The QE outputs handle the even pixels and connect to one of my SN65LVDS93B chips, while the QO outputs handle the odd pixels and connect to the other SN65LVDS93B. In this setup, each SN65LVDS93B processes only half the pixel data, effectively halving the PCLK for each chip.

    For 1920 x 1200 @ 60fps with 10% blanking, the approximate PCLK is ~152.064 MHz. Normally, if I connect Dual Channel LVDS, won’t this clock be split between the two SN65LVDS93B devices? Because in my mind, each device would see an effective PCLK of ~76.032 MHz, which is well within the 85 MHz limit for the SN65LVDS93B chips.

    The TFP401 provides a single clock output (ODCK) at ~152 MHz, which can be directly connected to the CLKIN pins of both SN65LVDS93B devices. Each SN65LVDS93B will process its respective even/odd data stream synchronized with this clock, ensuring everything stays in sync without the need for additional clock manipulation.

    The alternative would be to use 1-pixel/clock mode, where the TFP401 outputs all pixels sequentially. This would require dividing the TFP401 clock (152 MHz) by 2 and providing this divided clock to the SN65LVDS93B devices. However, I think this adds complexity, as it would need external logic for clock division and pixel sequencing. That's why in my mind 2-pixel/clock mode seems much simpler and better suited for this application.

    Let me know what do you think about it and if i am wrong Slight smile

    Best,

    Axel

  • 0 in reply to Axel Chaudron
    TI__Genius 10585 points

    Hi Axel,

    Thanks for your insights and detailed consideration!

    Axel Chaudron said:
    The QE outputs handle the even pixels and connect to one of my SN65LVDS93B chips, while the QO outputs handle the odd pixels and connect to the other SN65LVDS93B. In this setup, each SN65LVDS93B processes only half the pixel data, effectively halving the PCLK for each chip.
    Axel Chaudron said:
    For 1920 x 1200 @ 60fps with 10% blanking, the approximate PCLK is ~152.064 MHz. Normally, if I connect Dual Channel LVDS, won’t this clock be split between the two SN65LVDS93B devices? Because in my mind, each device would see an effective PCLK of ~76.032 MHz, which is well within the 85 MHz limit for the SN65LVDS93B chips.

    Yes, under these conditions I believe this could work for the use of the SN65LVDS93B devices. I am not sure if the effective CLK of the pixels is half of what the TFP401 is receiving when using 2-pixel/clock mode, this may need to be confirmed by TFP team.

    Axel Chaudron said:
    The TFP401 provides a single clock output (ODCK) at ~152 MHz, which can be directly connected to the CLKIN pins of both SN65LVDS93B devices.

    I believe the maximum frequency that can be used at the CLKIN pin of the SN65LVDS device is 85 MHz, in which this configuration may not work. I do agree that the devices could separately process the even and odd pixel streams, but the synchronization of the PCLK input to the CLKIN must match the data rate of the RGB input (in this case the effective PCLK of ~76.032 MHz).

    I would need the TFP team to confirm if the 1-pixel/clock or 2-pixel/clock will split the frequency in half on the even/odd pixel outputs. 

    Best,

    Miguel