DP83867IRPAP-EVM: Request for Schematic of DP83867IRPAP-EVM

Hi Devaraj,

Please refer to DP83867EVM User's Guide for schematics:

https://www.ti.com/lit/pdf/snlu176

Devaraj Malladad said:

we are using DP83867IRPAP for 1000Base-t RGMII communication, I'm able to detect the Ethernet and unable to establish the communication.

This looks like an RGMII timing issue to me. RGMII internal TX_CLK / RX_CLK skew timing can be adjusted through straps or register access.

Please try tuning RGMII delays through register 0x32 and 0x86 to meet RGMII timing requirements shown in Section 6.9 of datasheet:

0x32[1] to enable/disable RGMII transmit clock delay
0x32[0] to enable/disable RGMII receive clock delay
0x86[7:0] to tune TX_CLK or RX_CLK delay when enabled

Thank you,

Evan

Hey Even,

Thanks for the Response. I'm thinking that to start from the HW schematic. if everything looks good, will proceed further. 

I'm adding HW Design engineer to this loop.

Hi Devaraj,

Sounds good, please reach out if there are any queries on the schematic design.

Thank you,

Evan

Hello Even,

Here the schematic FYR, please walk through the same and let me know if you find anything.

Hi Devaraj,

Due to holiday, please expect feedback by 1/3.

Thank you,

Evan

Hi Devaraj,

Please see my feedback below:

• Connector-side MDI termination does not follow recommendation. Please adjust to follow this scheme:
  
• Straps look good to enable RGMII mode with auto-neg enable, all speeds advertised.
• Please confirm magnetics and crystal models follow requirements noted in Table 8-1 and Table 8-2 of datasheet

Thank you,

Evan

Thanks for the input, but the Ethernet is being detected, and we are unable to ping or communicate. Could the issue be due to the above recommendation not being implemented?

Hi Devaraj,

In the case with link up with communication failure, the cause is likely RGMII timing delays.

Please share register values for 0x32 / 0x86. For the first test, I recommend writing 0x32[1:0] to the opposite value.

Thank you,

Evan