TFP401A-EP questions

Carlton Blow

Other Parts Discussed in Thread: TFP401A-EP, TFP401

Hopefully there is someone from the factory who has knowledge of the TFP401A-EP visiting here.

Upon review of the datasheet and other associated information from TI some questions have come up regarding the TFP401A-EP.

- Does anyone know what the clock to out timing specification is for the image output bus (QE[ ], QO[ ], VSYNC, etc.) relative to the output clock (ODCK)? I presume that this varies depending upon output drive strength? I presume it is the same regardless the clock edge (rising or falling) used to clock out the image bus? For some reason the datasheet specifies setup and hold. I am used to setup and hold timing specifications being used for inputs and not for outputs.

- Does anyone know if EXT_RES requires anything? Some of the information suggests leave it unconnected as there already is an internal termination matching circuit within the part. Other information suggests connecting it up to something, what that something is, is not specified. For example resistor size, pull-up, or pull-down.

- Does anyone know if RSVD is supposed to be tied directly to the supply rail or if pulling-up to the supply rail is acceptable. There is only mention of tying it to the supply rail. If it is to be pulled-up, what values are acceptible?

- Does anyone know if it is preferable to pull-up or pull-down the STAG# input when the part is to operate in single pixel mode?

TIA!

Regards,

Carlton

over 13 years ago

0 RE over 13 years ago

TI__Mastermind 20985 points

Hi Carlton,

-Figure 4 describes output timing. In this case, the terms "setup" and "hold" time are used to describe how the device presents output data.
-You can leave EXT_RES unconnected. This is a little confusing, and the pin exists for backwards-compatibility reasons.
-RSVD can be directly connected to DVDD. If you tie through a resistor, 4.7k or 10k is fine.
-STAG# doesn't matter when in single pixel mode.

Also, keep in mind that it can be good practice to design a board with resistor population options, when you're unsure of how you'll want to tie certain inputs. Then your final decision will only change the BOM, and not the board design.

Best regards,
RE

0 Carlton Blow over 13 years ago in reply to RE

Prodigy 70 points

Ross,

Thank you for the reply!

So if I understand you correctly on the first point, the setup timing parameter is specifying a maximum time the data may be advanced relative to the selected clock edge being used and the hold timing parameter is specifying a maximum time the data may lag relative to the selected clock edge being used?

Regards,

Carlton

0 RE over 13 years ago in reply to Carlton Blow

TI__Mastermind 20985 points

Almost--it's actually specifying minimum times that the data will be valid, before and after the clock edge. The more time, the better, and the spec is how much is guaranteed.

Thanks,
RE

0 Carlton Blow over 13 years ago in reply to RE

Prodigy 70 points

Hi Ross,

Ok. That confirms what I was concerned about. The image bus is only valid for a tight window around the selected clock edge. Almost like the output stage is a latch or something as opposed to a register.

We are running our LCD at ~32MHz (ODCK) or so and the LCD requires at least 5nS setup and 5nS hold about the rising edge of the clock. I was hoping that I could select falling edge clock for clocking out the image bus to ensure meeting setup and hold on the rising edge of the clock at the LCD. Since the datasheet is only specifying image bus validity tightly about a clock edge, it looks like I will need a register between the TFP401A-EP and the LCD to ensure the image bus to be valid over a larger percentage of the clock period so that I can meet the setup/hold times of the LCD.

Thanks again!

Regards,

Carlton

0 RE over 13 years ago in reply to Carlton Blow

TI__Mastermind 20985 points

Hi Carlton,

The device might be able to meet 5ns at 32MHz. The specs for minimum output timing apply to the full frequency range of 25-165MHz, and it's worst-case at 165MHz (which has a period of 6ns). In that 6ns case, the device guarantees tsu1 > 1.8ns and th1 > 0.6ns. 32MHz has a 31.25ns period, and 5ns might be ok. I can look into testing this if you'd like.

Thanks,
RE

0 Carlton Blow over 13 years ago in reply to RE

Prodigy 70 points

Hi Ross,

Yes, please do and much appreciated!

For ODCK clock rate frequency, we will be running at 32.258 MHz (31nS) worst case. I gather that producing a resulting clock rate at this actual frequency/rate may not be practical. So if you need to go slightly higher for testing practicality please do so.

Thanks again!

Regards,

Carlton