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DP83TG721S-Q1: Cannot get alive response via MDIO bus

WeiTing Chou
Prodigy 80 points
Part Number: DP83TG721S-Q1

Tool/software:

Hi TI expert,

we try to bring up DP83TG721S-Q1 with TDA4AL.

Original, the code(lwip_example_freertos) can work with dp83867 successful on TI EVM(J721S2).

Therefore, we follow this pdk link to add DP83TG721S-Q1 eth phy.

However, I cannot get alive response via mdio bus.

I had check the wake up pin and INH pin is high.

The Schematic about mdio pin is follow evm design.

The mdio clock is 2.2Mhz.

How can I check this problem?

  • +1
    TI__Genius 14006 points

    Hi WeiTing,

    There are some documents on the DP83TG721 that are NDA. Can you reach out to your local TI field representative to help confirm NDA status and continue this conversion over email? Can you also try using the DP83TG720 RTOS driver on github? https://github.com/TexasInstruments/ti-ethernet-software

    Here are some general tips for debugging MDIO/MDC:

            0. Check PHY is functional. It is good INH is high, but also check CLK_OUT is 25 MHz and power supplies are up

    1. The incorrect PHY ID and PHY address may be accessed by the SW
      1. PHY Address depends on HW Strap Configuration (datasheet section 8.5.1 Strap Configuration)
      2. PHY ID is defined in register 0x3
    2. Check PHY power-up timing. You can check the power-up sequence with the timing requirements in section 7.6 of datasheet.

    Best regards,

    Melissa