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TDP0604: TDP0604 - DP_MODE bits in the DP_MODE_CONFIG Register

Part Number: TDP0604

Tool/software:

We need to set the DP_MODE bits  to 3h to select DisplayPort in the DP_MODE_CONFIG Register. The problem is that the value does not stick. We always read 0h.  The bits have the type listed as "RH/W". The "H" means Set or cleared by hardware.  What conditions would clear these bits ?

  • Hi,

    Is the RATE_SNOOP_CTRL bit being disabled? The DisplayPort mode is enabled when DP_MODE field (offset 0x31) is programmed to 0x3 and RATE_SNOOP_CTRL (offset 0xA bit 2) is disabled. 

    Can you please send the full TDP0604 register dump if the issue still not being resolved? 

    Thanks
    David

  • Here are the registers. Note the TDP0604 is working in DP mode even though the DP_MODE_CONFIG register is set to 0.  Please explain what register type "RH" means. Does it mean the TDP0604 is clearing this bit automatically because we have the RATE_SNOOP_CTRL bit set to 0 = enabled ?

    ADDR Name Value
    0x08 REV_ID 0x03
    0x09 PD_RST 0x00
    0x0A MISC_CONTROL 0x08
    0x0B GBL_SLEW_CTRL 0x34
    0x0C GBL_SLEW_CTL2 0x71
    0x0D GBL_CTL1 0xE3
    0x0E GBL_CTLE_CTRL 0x03
    0x10 DDC_CFG 0x00
    0x11 LANE_ENABLE 0x5F
    0x12 CLK_CONFIG1 0x03
    0x13 CLK_CONFIG2 0x00
    0x14 D0_CONFIG1 0x03
    0x15 D0_CONFIG2 0x00
    0x16 D1_CONFIG1 0x03
    0x17 D1_CONFIG2 0x00
    0x18 D2_CONFIG1 0x03
    0x19 D2_CONFIG2 0x00
    0x1A SIGDET_TH_CFG 0x44
    0x1C GBL_STATIS 0x00
    0x20 SCDC_TMDS_CONFIG 0x00
    0x31 DP_MODE_CONFIG 0x00

  • Hi,

    Does it mean the TDP0604 is clearing this bit automatically because we have the RATE_SNOOP_CTRL bit set to 0 = enabled?

    Correct, RH means Set or Cleared by hardware

    With the RATE_SNOOP_CTRL bit being set to enable, TDP0604 internal DDC buffer will snoop on the LV_DDC_SDA/SCL pins. But with LV_DDC_SDA/SCL pins not being used for DP mode, TDP0604 will snoop a value of 0. So even if you write a 0x03 to the DP_MODE bit, TDP0604 will overwrite it with the snooped value of 0.

    Thanks

    David