DP83867IS: DP83867IS can't link up.

Kazuya-san

Due to the US Christmas and New Year holiday, the response to your question will be delayed. We have assigned an engineer to this E2E thread and will look into your question when we return. Sorry for the wait and any inconvenience it may cause.

Thanks,

David

Hi Kazuya,

Are you able to read the register? If so, could you give me the following register information: 0x0004 and 0x0009.

You can disable 11Gbps through register 0x0009 and disable 10Mbps through register 0x0004.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your reply.

I will ask the register value to the customer and I will inform you as soon as I get it (Probably early January)

Thank you again and best regards,
Kazuya. 

Hi Kazuya,

I will wait for customer's feedback.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your waiting.

I got the register values from the customer as the follows.

1. Auto-Negotiation Advertisement Register(0x0004)=0x01E1
2. Configuration Register 1(0x0009)=0x1300

They want to fix the communication speed and type to 100BASE-TX Full Duplex only.
Should TX_HD, Te_FD and Te_HD bit in 0x0004h register be "0"?
And should 1000BASE-T FULL DUPLEX and 1000BASE-T HALF DUPLEX bit in 0x0009h register be "0" too?

Could you please give me your reply?

Thank you again and best regards,
Kazuya.

Hi Kazuya,

Could you program the following register to enable DP83867 in only 100BaseTX full duplex:

• Configure register 0x0009 = 0x0000
• Configure register 0x0004 = 0x0101

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your reply.

The customer checked whether DP83867IS can link up with 100BASE Full duplex mode
with 0x0004 = 0x0101, 0x0009 = 0x0000.
As the result, DP83867IS couldn't link up with .

They wrote the values to the registers you told me. 

After that, they have read the value in the registers(0x0004, 0x0009) out
and confirmed that the values are same as written data.

The followings are their register data.

Address  Data     Address  Data     Address  Data     Address  Data  
0x0000  0x2100, 0x0001  0x7949, 0x0004  0x0101, 0x0005  0x0000
                                (Original data: 0x0004  0x01E1, 0x0005  0x1300)                                                            
0x0006  0x0064, 0x0007  0x2000, 0x0008  0x0000, 0x0009  0x0000
0x000A  0x0000, 0x0010  0x5448, 0x0011  0x6802, 0x0012  0x0000
0x0013  0x0040, 0x0014  0x29C7, 0x0015  0x0000, 0x0017  0x0040
0x001E  0x0002

And as a additional information, they could fix the communication speed to 10BASE
when they changed the value in register, 0x0000 from 0x2100 to 0x0100 only.

If there is any data should be modified to fix 100BASE Full duplex mode,
could you please let me know?  

Thank you again and best regards,
Kazuya.

Hi Kazuya,

Normally the link drop are due to the signal quality.

100Mbps use two pair of cable and 10Mbps use only single pair of cable. If one pair of cable has more mismatch result in worse signal performance, sometime the PHY can only support 10Mbps instead of 100Mbps.

We do have layout checklist that you could refer to to check on the design:

• 2555.Industrial_PHY_Layout Review Checklist.xlsx

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your support.

I see. I will ask them to check their layout base on the checklist you attached.

And I attached a file about their waveform. 
Could you please take a look and please give me your answer to Q1~Q4 questions in this file?

Thank you again and best regards,
Kazuya.

Customer_waveform011025.pdf

Hi Kazuya,

• May I ask what is the peak to peak voltage for your NLP pulses?
• The signal seems a little bit noisy. Not sure if this is the probing issue on the MDI lines or based on the signal quality.

If possible, could customer also read 0x0225 after they link up in 10Mbps?

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Thank you,

Hillman Lin

Hi Hillman,

Thank you for your supports.

Please let me confirm the read address.
0x0225 address is not described in the device datasheet.

Is this address correct?

Thank you again and best regards,
Kazuya.

Hi Kazuya,

The register 0x0225 is in the troubleshooting guide. Please refer to the following documents:

• https://www.ti.com/lit/an/snla246c/snla246c.pdf?ts=1736966673645&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83867E

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your reply.

But the document says page 10 "In 10Mbps communication, please do not refer to the table for accurate measurement"

Is this register address "0x0225" correct?

Thank you again and best regards,
Kazuya. 

Hi Kazuya,

Sorry for the confusion. You are correct. 0x0225 does not apply for 10Mbps. 

I would say layout and signal measurement would be our approach to check the signal quaity.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your reply.

They checked their layout with your layout guideline. But they can not find any problem.

Is there possibility that the cable has any problem?
Also, if link up is success when shorter cable length, what is cause of link up failure.
Is it cable class?

Thank you again and best regards,
Kazuya.

HI Kazuya,

If you are able to link up with shorter cable, this is an indication of poor signal quality.

Long cable normally have higher attenuation and result in poorer signal quality and FLP. Measuring the signal on MDI lines on the scope could show this behavior.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your strong supports.

I understood what you said.
Could I ask you an additional question as the below?

Q.
How can they judge if their Ether signal quality is good or bad?
If they take the compliance test of Ether, can they know if their signal quality is good or bad?

Or is there any other way to judge?

Thank you again and best regards,
Kazuya.

Hi Kazuya,

Yes, compliance test would be a proof on the signal quality. I would go with compliance test approach if customer is able to run the compliance test.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your strong supports.

The customer want TI to check their current schematic.
But they don't want to disclose their schematic in this tread.
So I'd like to send you their schematic if you tell your e-mail address.

Could you please tell me your e-mail address if it is not problem? 

Thank you again and best regards,
Kazuya.

Hi Kazuya,

Sure, I added you as a friend you can send it to me through private chat.

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Regards,

Hillman Lin

Hi Hillman,

Thank you very much for your kind reply and telling your e-mail address to me.

I sent you their schematic yesterday by e-mail.
Could you please take a look the attached files and please give me your reply?

Thank you again and best regards,
Kazuya.

Hi Kazuya-san,

 I check it the schematics. It seems like customer is using the integrated RJ45 with the return loss and cross talk meeting the specification.

I am still more concerning on the layout standpoint:

• Making sure to have short trace length
• Making sure the trace is impedance matching

If possible, could customer connect with another DP83867 and see if they are able to link up in 100Mbps?

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Regards,

Hillman Lin

Hi Kazuya-san,

Based on the register read you provided, it seems like customer is not able to auto-negotiation successfully with 100Mbps.

• Did customer also have a register dump for 10Mbps?

If possible, may I ask what is the peak to peak of the FLP pulse during 10Mbps and 100Mbps?

I confirm with customer on the schematic, it seems like customer is using integrated RJ45 and the transformer spec. follow the schematic specification. I did not see any issue with the schematic.

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Regards,

Hillman Lin