Tool/software:
Hi Expert,
when switching from continuous to polling mode, my steps are: SPI write configuration. Set TRIGGER to 0h in the CONFIG register; then POLL_EN to 1h in the CONFIG register, INT_CONFIG to 1h ,POLL_TIME to 2h, Then set TRIGGER to 1h in the CONFIG register. The problem is that after the mode switch is complete, after TRIGGER is set to 1h, an interrupt will be generated, at which point, Immediate SPI communication Send a READ command to the INT_STAT register for the interrupt clear, will be an invalid operation and interrupt clear will fail. If, after the mode switch is complete, after TRIGGER is 1h, write a delay of 60ms followed by the SPI communication sending a READ command to the INT_STAT register to clear the interrupt. Interrupt cleared successfully.
So, I would like to ask how long it takes after the mode switch is complete (TRIGGER set to 1h) before the READ INT_STAT register command is executed? and what cause clear interrupt delay?
best regards,
jeff wang
