DP83867CS: SGMII connection to Arria 10 GX

Hi Mikko,

I am checking if there is a register configuration we can apply to increase transmitter Vcm.

So I understand correctly, is this the requirement you are concerned with meeting:

Relative to SGMII spec:

Regarding your questions:

1) AC coupling is required to properly bias the SGMII receiver pins.

2) We have not validated SGMII scheme to increase Vcm, so it will be difficult to provide recommendations here. I will look into this further and share any findings.

Thank you,

Evan

Hey Evan,

Yes I am concerned about how Arria 10 Vicm (1...1.6V) is met.

To clarify few things first,

1. AC-coupling, is it mandatory also for PHY SGMII TX pins? 

2. Does PHY has inbuilt 100Ω differential termination also for SGMII TX side? If yes, what is the idea of it?

  Usually termination should be near the receiver pins. At the moment we have 100ohm termination on Arria receiver side. Now there is double termination resistor on PHY SGMII TX side (one on PHY and one on Arria 10).

3. See attached picture to understand issues

Hi Mikko,

1) From my understanding, SGMII coupling capacitors are required at each device's receiver pins to properly bias the receiver independent of the transmitter's common-mode.

2) Internal transmitter termination is the same as image shown for LVDS - in series with the traces.

Thank you,

Evan

hey Evan,

1. For my understanding AC-coupling is needed mostly when transmitter DC offset is not on area which is fine for receiver.

2. Now I am confused, on my pictures resistors are in parallel. May I get picture which shows how PHY SGMII input/output looks like?

-Mikko 

Hi Mikko,

I agree with you for (1).

Regarding (2), internal termination follows this image, both on output and input side.

Do you have an evaluation module for Arria 10 GX with the SGMII pins accessible?

One possibility for evaluation is using DP83867ERGZ-S-EVM and connecting the SGMII pins to SoC.

Thank you,

Evan

Hey,

I have tested this earlier with Cyclone 10 GX which is very similar than Arria 10.

PHY SGMII TX voltage swing is about half (100R term internal on PHY and 100R in FPGA) compared to RX pins, see pictures below,

Hi Mikko,

Does Cyclone 10GX also spec a similar Vcm for its LVDS receiver?

Do you see any functional issues with communication when testing with Cyclone?

I am trying to understand further if this Vcm is a strict requirement by SoC for valid communication, as SGMII is typically independent from Vcm due to AC coupling.

Thank you,

Evan

Cyclone 10 GX and Arria 10 GX LVDS receiver spec is same.

We have not seen any functional issues so far with Cyclone 10.

-Mikko

Hi Mikko,

Mikko Ahvalo1 said:

PHY SGMII TX voltage swing is about half (100R term internal on PHY and 100R in FPGA) compared to RX pins, see pictures below,

I've confirmed this difference in swing between transmitter/receiver side is within spec limit for SGMII.

As you see no functional issues with Cyclone 10, I expect equivalent circuit can be used with Arria 10.

Please share any doubts here.

Thank you,

Evan

Hey,

This shoul be okey.

One question more,

How to data is transferred between Ethernet PHY and MAC with SGMII, when Ethernet link speed is 10Mbps?