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TCAL9539-Q1: What is the I/O state during I2C error?

Leo Ma
Expert 4196 points

Part Number: TCAL9539-Q1

Tool/software:

Hi expert,

Have a nice day!

About TCAL9539-Q1, what are the I/O states during I2C error or other fault cases? Is that Hi-Z, low or other?

Best Wishes,

Leo Ma

  • 0
    TI__Guru 65368 points

    Hi Leo,

    TCAL9539-Q1 does not have a fault mechanism / fail-safe mechanism. 

    What type of fault condition is the customer exploring? 

    Regards,

    Tyler

  • 0
    Guru 327330 points

    The I²C protocol itself does not have any error-checking mechanism.

    The device is a simple state machine that reacts to the signals on the SCL and SDA pins. When the signals are corrupted, then it is possible that commands are acted on by the wrong (or no) device, or that wrong values are read from or written to the wrong register.

    To reduce the risk of errors, isolate the SCL/SDA lines from each other and from other traces with high-frequency signals/noise, and use a high pull-up current (typically 3 mA).

  • 0 in reply to Clemens Ladisch
    TI__Expert 4196 points

    Hi Tyler, Clemens,

    Thank s for your replies.

    IN Datasheet 8.1, "The system controller can reset the device in the event of a timeout or other improper operation by asserting a low on the RESET input pin or by cycling the power to the VCC pin and causing a power-on reset (POR). "

    What I want to know is what are the states of P00-P07 and P10-P17 before "asserting a low on the RESET input pin"? Such as Hi-Z, low or other?

    Best Wishes,

    Leo Ma

  • +1 in reply to Leo Ma
    TI__Guru 65368 points

    Hi Leo,

    The P00-P07 and P10-P17 pins will be set to their most recent configuration. This device does not have a specific IO configuration that results in case of a timeout or other error. 

    Regards,

    Tyler