DP83825I: Timing requirements as described in the datasheet

Masaki Takeuchi

Prodigy 450 points

Part Number: DP83825I

Tool/software:

Hi Team,

I have a question about the contents of the data sheet(Rev. A).

6.6 Timing Requirements

Regarding T4 of POWER-UP TIMING, it says within 50ms from the rise of power supply (VAVDD) to the rise of MDC.

I assume this is a description of the stability time after the power supply rises, but isn't this requirement more than 50ms? (min:50ms)
What is the intention of the rating?

6.6 Timing Requirements

Regarding T2 of RESET-TIMING, it is stated within 2ms to the rise of MDC after RESET is released.
Does this mean that the rise time of the next MDC must be within 2 ms after the reset is released? (Does it matter if MDC is input before the reset is released?)

Best Regards,

Masaki Takeuchi

8 months ago

+1 Gerome Cacho 8 months ago

TI__Mastermind 39855 points

Hello Takeuchi-san,

Q1) You may look at it that sort of way. This specification is meant to describe the pause needed post supply ramp-up for the SMI to be available. This time period is at most 50ms.

Q2) This means that SMI access is not available for 2ms post reset.

If SMI access is made during these "unavailable" durations, the PHY may be placed in an unexpected state. Thus it is important to obey these specifications.

Sincerely,

Gerome

0 Masaki Takeuchi 8 months ago in reply to Gerome Cacho

TI__Prodigy 450 points

Hi Gerome,

Thank you very much.

Best Regards,

Masaki Takeuchi

0 Masaki Takeuchi 8 months ago in reply to Masaki Takeuchi

TI__Prodigy 450 points

Hi Gerome,

Let me clarify,

-Regarding T4 of POWER-UP TIMING, does it mean that 50ms or more is required from the rise of power supply (VAVDD) to the input of MDC?

-Regarding T2 of RESET-TIMING, does it mean that at 2ms or more is required from the release of reset to the input of MDC?

Best Regards,

Masaki Takeuchi

+1 Gerome Cacho 8 months ago in reply to Masaki Takeuchi

TI__Mastermind 39855 points

Hi Takeuchi-san,

Q1) Yes, this is correct. Please ensure atleast 50ms or more is allocated after AVDD and VDDIO are stable.

Q2) This is also correct. Please ensure that after resetting during normal operation that SMI is accessed atleast 2ms after reset release.

Sincerely,

Gerome

0 Masaki Takeuchi 8 months ago in reply to Gerome Cacho

TI__Prodigy 450 points

Hi Gerome,

Thank you very much for confirming.

Best Regards,

Masaki Takeuchi

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DP83825I: Timing requirements as described in the datasheet