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DS32EL0124: Choosing the right interface chip to aggregate signals

Avner Cohen
Intellectual 460 points
Part Number: DS32EL0124
Other Parts Discussed in Thread: LMH0341, , DS25BR100, DS32ELX0124, LMH0397, DS90UB913A-Q1

Tool/software:

Hi ,

First, I have to mention that this query is general and not specific to the chip in the title.

Ti does not provide a way to ask an E2E question without choosing the device.

So please forward this request to support that that specialize in broad number of devices by Ti and not only this SERDES.:

 

I am Looking for TI Chip that will best fit to the following application. (see attached block diagram)

The requirement is to pass different signals with different bandwidth and asynchronous to each other, on a single coax.  The way is to aggregate them and pass then on single Coax cable that farther on will pass via rotary joint or slip ring devices. Thus, reducing the rotary joint and slipring size/nodes/cost comparing to passing them without the aggregation.

.

It is preferable to have the chip to be bidirectional so to have TX and RX on the same coax. So that single coax will be used.

The maximum aggregate rate can be less then 200Mbps but prefer to have 1G to 3Ghz rate.

 

I have added the block diagram of the solution that based on FPGA that on the TX side samples the signals/buses and put them on a single output. That output together with clock will be fed to TI chip that you will recommend me and will interface to the coax cable.

On the Rx side the chip will receive the data from the coax cable and provide the FPGA with the recovered data and recovered clock , the FPGA will extract the data from the aggregate input and recover all the signals.

The length of the cable is max 3 m. But I will prefer the chip to have pre-emphasis and on the receive side equalizer.

Also, in order to have eliminate DC on the line scrambler and de-scrambler is needed.

 

Please suggest a chip (for Tx, and for RX)  that can best fit to this application.

(chips that I have check but not really fit are the   : DS32EL0124 , DS32ELX0124, LMH0341/041/071/051 or the LMH0397, DS25BR100 none of them seems to match)

 

Note that the application requires clock to sample the incoming signals and need to be recovered on the other side, That is the reason that I hardly see the   FPD link 3 serializer DS90UB913A-Q1

As a candidate)

 

Also note that the application is not for video transfer and the aggregated data is not coded at all. (for example, it is not SMPTE compliant)

Thanks,

  Avner

  • 0
    TI__Mastermind 20901 points

    Hi Anver,

    Thank you for posting your inquiry to the TI E2E forum.

    We want to make sure we understand your request to best help you. Could you please help us to verify the following:

    • The device could be either a bi-directional or uni-directional SERDES
    • The FPGA will be transmitting/receiving multiple channels/lanes of data which may be asynchronous to each other.
    • Is the clock which is being sampled synchronous to any specific lanes of data which are being carried by the COAX?

    Best,
    David

  • 0 in reply to David Waier
    Intellectual 460 points

    Hi David,

    Here are the answers:

    • The device could be either a bi-directional or uni-directional SERDES è prefer bidirectional. However, if it is not possible to have it bidirectional, I will go for unidirectional times 2, which make it twice the price.
    • The FPGA will be transmitting/receiving multiple channels/lanes of data which may be asynchronous to each other. è yes. The signals as mentioned are not synchronous to one another. Several inputs may be RS422 that will be sampled to be aggregated.
    • Is the clock which is being sampled synchronous to any specific lanes of data which are being carried by the COAX? è No. the clock is being fed to the FPGA just to enable sampling of the various signals and to be able to recover them on the de-mux side. Its frequency though needs to be high enough to sample well the highest input and that is dependent on the chip that you will suggest. Preferably in the range of 500 Mhz<f < 2Ghz  

    Looking forward to your suggestion for IC.

  • 0 in reply to Avner Cohen
    TI__Mastermind 20901 points

    Hi Anver,

    Thank you for some additional inputs of your system's requirements.

    Please allow me to share this ticket with another team at TI who may be able to help to provide a more appropriate solution for you.

    Best,
    David

  • 0 in reply to David Waier
    TI__Genius 13230 points

    Hi Avner,

    What type of data is the SERDES expecting to receive and send? I only se TXCLK and RXCLK.

    Best Regards,

    Gil Abarca

  • 0 in reply to Gil Abarca Ramos
    Intellectual 460 points

    Hi Gil,

    The Overall system should pass various signals from simple discretes with rate of change of seconds, RS422/ RS232 serial communication of rate of 115200 Hz, and if the serdes should be fast enough even to pass higher signals such as CAN bus or even ethernet up to 100M.

    The serdes may have several ports. All of them will come from the FPGA.

    Now the method I thinking of, is to sample the signals inside the FPGA, the slower ones,  such as discretes to aggregate  into  single line,  other signals which are faster will be just sampled and passed to the SerDes.

    The SerDes function will be to be able to interface coax line and to be able to recover the data using CDR also to make sure the data will be scrambled so to reduce DC bias so in order to properly recover the data passed on single coax.

    If possible to have both TX and RX on the same coax otherwise to have the system doubled and have 2 coax lines one for RX and the second for TX.

    Does that makes sense ?

    Since the purpose of the design is to make the slipring removed, or make it smaller in capacity of signals transferred, there is no streak restrictions. Any major reduction of signals having our best effort will be acceptable.

    Thanks

     Avner

  • 0 in reply to Avner Cohen
    TI__Genius 13230 points

    Hi Anver,

    We have a serdes that accepts parallel data and output parallel data. Can you take a look at DS90UB925-Q1 and DS90UB926-Q1. SInce they are parallel input then it should allow you to pass any signal and not just RGB data.

    Best Regards,

    Gil Abarca