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TMUXHS4412: Inquiry about the usage of TMUXHS4412 Single-Ended

Part Number: TMUXHS4412
Other Parts Discussed in Thread: HD3SS3411, TS3USB31E, TMUXHS221, HD3SS3212, TS3USB221, HD3SS6126

Tool/software:

Hello,

This is an inquiry regarding the usage of the TMUXHS4412 Single-Ended.

We are considering using it in connection with the FPGA's IO channels.

Depending on the operational functions of the FPGA, we are planning to use the same channel as shown in the image below. Could you please confirm if this is possible?

  • Hello,

    You could use these pins for GPIO, yes. Typically, we only recommend using the positive lane if you are going to send a single-ended signal through the channel. The negative lane can be left floating.

    Another thing to keep in mind with these channels is the max supported voltage on the I/O. This mux cannot support signaling up to 3.3V if needed.

    I would just like to clarify, with these signals listed in the image, are you saying the lane will send diff CLK, and sometimes switch to other signals? Or are you just trying to determine what signals each channel can send?

    Thanks,

    Ryan

  • Hello,

    Thank you for your response.

    The voltage of the signal is below 1.8V.

    As described in the blue text of the image mentioned in the previous question, the FPGA output switches signals on the same channel depending on the function settings.

    The FPGA channel is configured to switch between Diff CLK, Single CLK, and GPIO functions depending on the usage scenario.

    If only the positive channel is used and the negative channel is left floating, is it possible to use the CLK signal down to the DC level?

    I am wondering if connecting only the positive channel to the FPGA would allow the use of Diff CLK, Single CLK, and GPIO (DC level) altogether.

    Additionally, we are currently reviewing replacement options.

    Could you recommend a single-channel MUX part that meets the condition of Fmax < 3GHz?

    Thank you.

    Jun-Seok

  • Hi Jun-Seok,

    The FPGA channel is configured to switch between Diff CLK, Single CLK, and GPIO functions depending on the usage scenario.

    I believe this use case would be okay.

    If only the positive channel is used and the negative channel is left floating, is it possible to use the CLK signal down to the DC level?

    How do you mean? Like, have the CLK signal no longer alternating to where it is just a flat voltage/current?

    I am wondering if connecting only the positive channel to the FPGA would allow the use of Diff CLK, Single CLK, and GPIO (DC level) altogether.

    For any differential signaling, the negative signaling would require a second channel, such as D0N. P/N differential signaling should stick to their respective lanes.

    Additionally, we are currently reviewing replacement options.

    Could you recommend a single-channel MUX part that meets the condition of Fmax < 3GHz?

    For lower frequency single-channel muxes, I believe our only option is the TS3USB31E, which is rated for USB2 at 480Mbps. We also have the HD3SS3411, which is rated for USB3 at 5Gbps.

    Other than that, we have some 2:1 muxes, such as the TS3USB221 or the TMUXHS221 for USB2, or the HD3SS3212 or the HD3SS6126 for 10Gbps USB3.

    Thanks,

    Ryan

  • Hi Ryan

    jun - seok bae said:

    If only the positive channel is used and the negative channel is left floating, is it possible to use the CLK signal down to the DC level?

    How do you mean? Like, have the CLK signal no longer alternating to where it is just a flat voltage/current?

    It was a question about whether it is possible to use it as shown in the image below.

    We are reviewing the alternative part TMUXHS221.

    Your response was very helpful.

    Thank you.

    Jun-Seok