DP83TG720R-Q1: Rise time

Hi Daniel,

Slew rates under different drive levels are given in the datasheet.

VDDIO level will not affect the slew rate.

Thanks,

David

Hello, Creger. 

I saw the different slew rate driver level the slow one is <0.75ns for RGMII. But the requirement of RGMII on board systerm level(including driver, trace, serial resisrtor, receiver side ) should be meet within 0.75ns. why TI design give slower option for driver level?

Hello David,

1. According to screenshot, both medium slew and slowest slew max value exceed 750 ps, but rise time requirement should be lower than 0.75 ns, this is a conflict, causing customers cannot choose medium and slowest.

2. For DP83TG720R, there three Rseries level matching different mode in datasheet, and 3 corresponding modes in IBIS model. But for 812R, there is only one Rseries, can you confirm which mode it belongs to? In IBIS model there are slow and default mode, which are not matched. Pls confirm.

	Datasheet	IBIS Model
812R
720R

3. Customer needs to do P2P compatible for 720R and 812R, but it is obviously the Rseries is not same, which will influence the external design, causing customer cannot achieve drop-in replacement.

Pls check the questions above, thanks!

Regards,

Daniel Wang

Hi Daniel, Jing, 

1. Option for slower rise/fall time is given as it is beneficial for EMC concerns. If <0.75ns is required, please use the default mode.

2. Mechanism for changing slew rate of MAC interface is different between 720 and 812. Integrated MAC series termination is adjusted for 720, but not for 812. This is why 720 shows 3 rseries levels but 812 shows only 1.

3. 720 and 812 are not pin to pin compatible. They are footprint compatible and will require BOM changes to switch between the two. Series MAC resistors can be adjusted between the two devices if needed. We recommend to conduct IBIS model simulation to determine if series resistors are needed in each case.

Thanks,

David

For dp83tc812r-q1,  there are 5 bit for mac_rx_impedance_ctrl in IO_MUX_CFG Register (Address = 456h) [Reset = 0000h] , I saw 0b is reset value, does it mean 0b is default value which is corresponding with below R series integrated in PHY IC?

And if only 1 drive level, why IBIS show 2 driver level in dp83tc812r-q1 IBIS model? pls clarify which one in IBIS is the correct one to use.

Hi Jing,

Please see this FAQ. This FAQ describes Slow mode and fast mode, which you see in the IBIS models.

Thanks,

David

Hello David,

Can you help check the 720R registers matching with IBIS as below table, are they correct?

Thanks!

Regards,

Daniel Wang

the FAQ you show is dp83tc812S-q1, does it same with dp83tc812r-q1? on drive level?

Hi Jing,

For 720R, "default mode", "medium slew", and "slowest slew" in the IBIS file correspond to the below modes in the datasheet.

the FAQ you show is dp83tc812S-q1, does it same with dp83tc812r-q1? on drive level?

Yes, the same applies for 812R and 812S.

Thanks,

David