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TLK10232: Question related to the internal switch usage

Joerg Hopfe
Prodigy 40 points
Part Number: TLK10232


Tool/software:

We have the TLK10232 sitting on an extender board to one of our switches - the TLK is connected to 2 XAUI interfaces on its LS side and to a processor with 10G-KR on its HS side.

During bring up of the extender board (and maybe also later on in the real application) we need to have the option to interconnect the 2 XAUI interfaces, i.e. bridging LS channel A IN to LS channel B OUT and LS channel B IN to LS channel A OUT respectively. Acc. to our interpretation of the data sheet this should be possible using the internal switch function of the TLK10232. The idea is, that this XAUI bridge on the LS side is possible regardless of the state of the KR interfaces on the HS side. The switch should be controlled by MDIO register access (i.e. not Pin controlled).

Could you please advise,

* if the intended functionality is supported by the TLK10232 device

* which register values should be used to configure this

* which limitations or special conditions/dependencies would have to be considered (if any).

Thank you very much in advance for feedback & support!

BR
Joerg

  • 0
    TI__Mastermind 29090 points

    Hi Joerg,

    Yes, the data switch can be used to interconnect 2 XAUI interfaces. The registers to configure this are 0x0017 to 0x001A.

    Do you wish to use pin PRTAD0 to switch between KR to XAUI and XAUI to XAUI configurations? Or do you wish to use MDIO writes to switch between configurations? I can share register values based on your switching preference.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 40 points

    Hi Lucas,

    Thanks for your reply. As mentioned the switch should be based on MDIO writes and should be independent from the KR status.

    BR
    Joerg

  • 0 in reply to Joerg Hopfe
    TI__Mastermind 29090 points

    Hi Joerg,

    I understand, thank you for point this out. Please try the following register writes.

    Both channels A and B:

    • 0x0019=0x2500
    • 0x001a=0x8c20

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 40 points

    Hi Lucas,

    Thank you for your feedback. In general it appears to work. However, I had to configure 0x001a to 0xac20 for the switch to occur. Does this make sense?

    Another question: Does this switch constellation include the FIFOs to compensate for any clock deviations between the 2 XAUI channels and the refclk?

    There are a few other points to clarify (e.g. LVPECL circuit for REFCLK) and I'm goin to open a separate post for this.

    Thanks.

    BR
    Joerg

  • 0 in reply to Joerg Hopfe
    TI__Mastermind 29090 points

    Hi Joerg,

    I'm still looking into this and will get back to you with feedback by early next week.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 40 points

    Hi Lucas,

    Thanks for your reply. Looking forward receiving further feedback from you.

    Meanwhile we have been testing another approach for the "XAUI bridge".
    On both channels we configure:
    reg 1E.000B 0x0D11 // Enable shallow local loopback mode
    reg 1E.001A 0xEC20 // Select alternate channel HS output

    The result is the same regarding FCS errors.
    CHANNEL_STATUS_1 (1E.000F) reports 0x748f on both channels. Not quite sure if this was read multiple times (to deal with any latched bits).
    However, if it would be '1' for consecutive reads the TX-Underflow (bit 7) may give us a hint?

    Please comment on this scenario too.

    Thank you very much for your support.

    BR
    Joerg

  • 0 in reply to Joerg Hopfe
    TI__Mastermind 29090 points

    Hi Joerg,

    Thank you for sharing this update. I'm still working on this and will get back to you early next week.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Mastermind 29090 points

    Hi Joerg,

    My apologies for the delay.

    Using 0x001a=0xac20 makes sense to me. The original register value I provided waits for an IDLE on all lanes to trigger the data switch. 0xac20 triggers the data switch on any data.

    Using this method to data switch does include TX CTC and RX CTC FIFOs in the data path.

    Using shallow local loopback includes more functional block in the data path, which could increase latency. I don't immediately see an issue using this configuration either.

    I'll keep FIFO underflow discussion in your other E2E thread.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 40 points

    Thanks, Lucas.

    You worte that "Using this method to data switch does include TX CTC and RX CTC FIFOs in the data path." but your drawing appears to exclude TX-CTC.
    If you could definitely state what is true, then I think we can close this thread and handle the remaining issues in the other one.

    Thanks again.

    BR
    Joerg

  • 0 in reply to Joerg Hopfe
    TI__Mastermind 29090 points

    Hi Joerg,

    Sorry, that's my mistake. the signal path only includes RX CTC.

    Best,

    Lucas