Tool/software:
Hi,
At the DP83867ERGZ datasheet the power shows that the clock should be running prior to the VDD, but it doesn't show how long before VDD is stable.
Can anyone tell me if it's critical that the clock will be running prior to VDD ?
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Tool/software:
Hi,
At the DP83867ERGZ datasheet the power shows that the clock should be running prior to the VDD, but it doesn't show how long before VDD is stable.
Can anyone tell me if it's critical that the clock will be running prior to VDD ?
Hi Yoel,
Clock must be available at power ramp for PHY to power correctly.
If it is not available, it's recommended to hold RESET_N low and release it at least 100us after clock is stable.
Thank you,
Evan