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LMH1218: Inquiry About SDA/SCL Capacitance Values for LMH Series ICs

Diego Shinji Kawaguchi
Prodigy 140 points
Part Number: LMH1218
Other Parts Discussed in Thread: LMH0397, LMH1219,

Tool/software:

Hi team,

Could you please provide the maximum “Capacitance for SDA and SCL pin” for the I2C bus that includes TI’s LMH1218, LMH1219 and LMH0397 devices?

I’m trying to determine the appropriate pull-up resistor values for this I2C bus, but I can’t calculate the rise time accurately without knowing the capacitance specifications for SDA and SCL.

If these capacitances can be derived from other parameters in the datasheet, could you also explain how to perform that calculation?

Thank you for your assistance.

Best Regards,

Diego

  • +1
    TI__Genius 9209 points

    Hi Diego,

    While I do not have data on the maximum capacitance for the SDA and SCL pin, I have referenced all the EVM schematics for a reference of what pull-up resistor value we use for the devices and they are all 2k ohms.

    Looking at the SMBus spec and our datasheet, I see that the pull-up resistor value can be within a range depending on the bus capacitance, and the flexibility of the spec itself. TI recommends a pull-up resistor of between 2k and 5k ohms for the devices you listed above.

    Best Regards,

    Nick

  • 0 in reply to Nick Peabody
    Prodigy 140 points

    Dear Nick,

    Thank you for reviewing all the EVM schematics and providing the pull-up resistor recommendations.

    I appreciate your assistance.

    Best regards,

    Diego

  • 0 in reply to Nick Peabody
    Prodigy 140 points

    Dear Nick,

    I have an additional question.

    Given that my I2C bus connects multiple ICs and involves long wiring, I am concerned that the increased load capacitance may lead to longer rise times if the pull-up resistor values are not appropriately adjusted.
    Currently, in the absence of specific capacitance values for these ICs, I have estimated each to contribute approximately 10 pF to the bus.

    Could you please advise if this estimation is reasonable and provides sufficient margin for reliable operation?

    Thank you for your assistance.

    Best regards,

    Digo

  • 0 in reply to Diego Shinji Kawaguchi
    TI__Genius 9209 points

    Hi Diego,

    Greetings to Japan.

    I would recommend using the 2K pullup value.

    Best Regards,

    Nick

  • 0 in reply to Nick Peabody
    Prodigy 140 points

    Dear Nick,

    Thank you for your response.

    I realize that my question may not have been clear, so I would like to clarify the reasoning behind my inquiry.

    When calculating the range of possible pull-up resistor values, the most stringent upper limit is determined by ensuring that the rise time remains within 300 ns, given the total load capacitance of the I2C bus.

    Specifically, in a certain I2C bus configuration, including wiring capacitance, the total load capacitance is approximately 346 pF.
    Based on the transient response equation, the pull-up resistor value must be 1.023 kΩ or lower, so we plan to use 1 kΩ pull-up resistors for this bus.

    However, since the capacitance of some ICs is unknown, I have estimated each of them to contribute 10 pF to the total bus capacitance.
    If the actual capacitance of these ICs is higher than our estimate, the rise time could exceed 300 ns, leading to a potential timing issue.

    This is why I am seeking confirmation on whether assuming 10 pF per IC provides a sufficient margin for reliable operation.
    I would appreciate it if you could investigate this matter further.

    Thank you for your assistance.

    Best regards,
    Diego

  • 0 in reply to Diego Shinji Kawaguchi
    TI__Genius 9209 points

    Hi Diego,

    Thank you for the clarification. I honestly do not know in this case. I will have to check with our SMBus design team and get back to you. Please allow me some time (early next week) to verify for you. 

    I appreciate your patience and thank you for bringing this up.

    Best Regards,

    Nick

  • +1 in reply to Nick Peabody
    TI__Genius 9209 points

    Hi Diego,

    I checked and I found that: Typical loading capacitance for SDA or SCL is less than 5pF. You can use 5pF plus some margin like 25% for his analyses(for example 7pF). So the maximum capacitance for 16 devices would be 112 pF (7*16).

    Best Regards,
    Nick

  • 0 in reply to Nick Peabody
    Prodigy 140 points

    Dear Nick,

    Thank you for checking and providing the details.

    I will proceed with the 7 pF estimate per device, as you suggested, and calculate the total capacitance accordingly.

    This will help refine the pull-up resistor selection for the I2C bus.

    I appreciate your support.

    Best regards,
    Diego