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DS90UB914A-Q1: Lock time

Shuji Ishiwata
Mastermind 8160 points
Part Number: DS90UB914A-Q1


Tool/software:

Hi All,


I have a question about LOCK on the DS90UB914A-Q1.

As stated in the datasheet below, in 12-bit LOW-Frequency mode, PCLK becomes active before the LOCK signal goes high.

(1) Please tell me how long it takes for the LOCK signal to go high after PCLK becomes active.

(2) Am I correct in understanding that the PCLK signal generated by the deserializer IC is finalized before the LOCK signal goes high?

Best Regards,
Ishiwata

  • 0
    TI__Mastermind 28470 points

    Hello Ishiwata-san,

    We do not have a spec for the time between lock and PCLK, but  the total deserializer lock time will range from 15ms to 22ms. When operating in 12bit HF mode, the lock signal is tied to the serializer receiving a valid PCLK, other modes do not have this dependency. Also note that these devices do not modify any input data and simply output the received serializer data unchanged.

  • 0 in reply to Darrah Merillat
    Mastermind 8160 points

    Hello Darrsh-san,


    Thanks for your answer.

    You said that the total lock time of the deserializer is 15-22msec.

    What is the starting point of 15-22msec? Is it the time from when the PCLK is recognized to when it locks?

    Also, when operating in 12-bit HF mode, the lock signal depends on the PCLK from the valid serializer, but in other modes such as HL mode, the PCLK from the serializer is output directly through the deserializer regardless of lock.

    Is this understanding correct?

    Best Regards,
    Ishiwata

  • +1 in reply to Shuji Ishiwata
    TI__Mastermind 28470 points

    Hello Ishiwata-san,

    The total lock time is the time between the device PDB going high and lock. Yes, the device is able to output PCLK prior to lock stabilizing. This is with regards to start-up of the device and when each signal will go high. 

  • 0 in reply to Darrah Merillat
    Mastermind 8160 points

    Hello Darrsh-san,


    Thanks for your reply and support.

    I would like to clarify the contents. Is my understanding of the following correct?

    - When operating in 12-bit HF mode, the PCLK signal is output before the Lock signal is asserted, but a stable PCLK signal (correct PCLK signal) is not obtained until the Lock signal is asserted.
    - In 12-bit LF mode and 10-bit mode, there is no dependency between the Lock signal and the PCLK signal. Therefore, a stable PCLK is obtained before the Lock signal is asserted.


    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 28470 points

    Hello Ishiwata-san,

    In 12-bit LF and 10-bit mode, the PCLK signal will be output before lock. In 12-bit HF, the PCLK signal will be output at the same time as lock. In both cases the output signal is stable, only the timing in relation to the lock signal is different.

  • 0 in reply to Darrah Merillat
    Mastermind 8160 points

    Hello Darrsh-san,

    Thank you for your answer.

    In 12-bit LF mode and 10-bit mode, can I understand that if the Lock signal is asserted, a stable PCLK signal is output?

    Also, can I understand that the output PCLK signal is a stable PCLK signal regardless of the Lock signal?

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 28470 points

    Hello Ishiwata-san,

    Yes, but I do want to point out, this is assuming that the rest of the system is operating as expected. For example if the camera/imager sourcing the data is not sending a valid PCLK then the deserializer will not correct the PCLK signal.

  • 0 in reply to Darrah Merillat
    Mastermind 8160 points

    Hello Darrsh-san,


    Thank you for your answer.

    I'm very sorry that I asked the question poorly.

    Which one did your answer "yes" refer to?

    ・In 12-bit LF mode and 10-bit mode, can I understand that if the Lock signal is asserted, a stable PCLK signal is output?
    ・output PCLK signal is a stable PCLK signal regardless of the Lock signal?


    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 28470 points

    Hello Ishiwata-san,

    In 12-bit LF mode and 10-bit mode, a stable PCLK will become available before the Lock signal is asserted. In 12-bit HF mode, a stable PCLK will become available when the Lock signal is asserted.

    Regardless of the mode, the device is only outputting the PCLK signal that is being received by the serializer. The device does not generate a new or modified PCLK signal.