TCAN4550-Q1: Busrt Transfer of CAN data

Hi Ankita,

The TCAN4550 boosterpack module includes demo code for use with the TI MPS430 MCU. The SPI drivers in this demo code are pretty basic and should be a good reference for implementing burst writes and reads in your system.The demo code can be downloaded from the boosterpack's store page at the link below:
https://www.ti.com/tool/BOOSTXL-CANFD-LIN#order-start-development 

The SPI header and .c files can be found in the TCAN4x5x folder in the project. The .c implementation will need to be updated to use the correct syntax for the SPI hardware addresses on the iMX8DXL. Let me know if you have any questions on the concepts shown in the demo code here or how they relate to the information described in the documentation for TCAN4550. 

Regards, 
Eric Schott

Hi Ankita,

Thanks for your patience on this.

The demo code for the TCAN4550 only includes the basic read and right methods for 32-bit transactions. A new function would need to be defined to transmit or receive multiple words in a single transaction. We can use the existing START, WRITE/READ, and END functions within this new method to make things easier. An example of a function to write multiple words to TCAN4550 is below:

/*
 * @brief Dynimc multi-word write
 *
 * @param address A 16-bit address of the destination start register
 * @param data A pointer to array containing data of 32-bit words to write to the destination and subsiquent registers
 * @param words The number of words to write at once, values 0-255
 */
void
AHB_WRITE_N_WORDS(uint16_t address, uint32_t * data, uint8_t words)
{
    uint8_t i = 0;
    AHB_WRITE_BURST_START(address, words);
    while(i < words)
    {
        AHB_WRITE_BURST_WRITE(*(data + i++));
    }
    AHB_WRITE_BURST_END();
}

The corresponding method for a burst read will look very similar to this write example. However the way that the read data is returned will depend on whether the software designer prefers to pass data by reference or by value. Let me know if there are specific questions on how this may work.

I'm not familiar with the MCU mentioned here and dealing with multithreaded processors is a bit outside of my expertise. I would recommend contacting the support team for that device for help with isolating communication to a single core. 

Regards, 
Eric Schott