I'm referencing the TLK100 datasheet (SLLS931B–AUGUST 2009–REVISED DECEMBER 2009) and my question involves the PHYAD[0:4] lines. Page 6/88, Table 2.2 shows MII_COL/PHYAD0 being internally pulled UP by default while all the other PHYAD[1:4] pins are pulled DOWN. Then, on page 8/88, Table 2.7 lists PHYAD[4:0], specifically including PHYAD0(MII_COL), as having all internal pull DOWN resistors. Then, on page 15/88, it shows the default setting for PHY address as being 0x0h with all internal pull DOWNs; however, the figure below (Figure 3-1) shows PHYAD0 being internally pulled UP by default (with a conflicting note above the figure, might I add.).
I simulated the IBIS model for the TLK100 in HyperLynx and verified that PHYAD0 is internally pulled UP and PHYAD[1:4] are internally pulled DOWN. Given the several inconsistencies, I'm sure you can understand my confusion/hesitation, but I am designing under the following assumption: PHYAD0 is internally pulled up by default and PHYAD[1:4] are pulled down by default. Is this a correct assumption?
Thanks in advance for your time and help!!
