DP83822I: Trigger a hard reset using a GPIO

Benjamin Postma

Part Number: DP83822I
Other Parts Discussed in Thread: AM6442, TPS65220

Tool/software:

Dear community,

I'm working on a custom board based on a TI AM6442 SOC with two PHYs DP83822 connected. For power management we use a PMIC TI TPS65220.

The reset (NRESET) of each PHY is routed to a GPIO at the AM6442 (external pull-up to 1.8V). Since reset of the PHYs are high (= no reset) at startup, and the AVD changes during boot (2.5V initial at LDO4 -> 1.8V after PMIC configuration), we must reset the PHYs after changing the power, so that they will reinitialize completely, including the bootstrapping pins.

I looked at some examples and the documentation (ethernet-phy.yaml), but I was not able to trigger a reset, preferably via sysfs.

My device tree node looks like the following:

mdio1_pins_default: mdio1-default-pins {
	bootph-all;
	pinctrl-single,pins = <
		AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
		AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
	>;
};
	
cpsw1_rst_default: cpsw1_rst_default_pins {
	pinctrl-single,pins = <
		AM64X_IOPAD (0xBC, PIN_OUTPUT, 7) /* (U8) PRU0_GP_1 / GPIO0_46 */
	>;
};

cpsw2_rst_default: cpsw2_rst_default_pins {
	pinctrl-single,pins = <
		AM64X_IOPAD (0xE8, PIN_OUTPUT, 7) /* (U9) PRU0_GPO_2 / GPIO0_57*/
	>;
};
	    

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio1_pins_default>, <&cpsw1_rst_default>, <&cpsw2_rst_default>;

	cpsw3g_phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0>;
		reset-names = "phy";
		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
		reset-assert-us = <1000>;
		reset-deassert-us = <2000>;
		rx-internal-delay-ps = <1>; 
        tx-internal-delay-ps = <1>; 
	};

	cpsw3g_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		reset-names = "phy";
		reset-gpios = <&main_gpio0 57 GPIO_ACTIVE_LOW>;
		reset-assert-us = <1000>;
		reset-deassert-us = <2000>;
		rx-internal-delay-ps = <1>;	
        tx-internal-delay-ps = <1>;
	};
};

So my question is, how can I trigger a complete reset of the PHYs?

Any help is appreciated.

BR Benjamin

10 months ago

0 Gerome Cacho 10 months ago

TI__Mastermind 40285 points

Hi Benjamin,

Thanks for the post. One of our engineers will be with you shortly.

Sincerely,

Gerome

0 Evan Mayhew 10 months ago in reply to Gerome Cacho

TI__Mastermind 25148 points

Hi Benjamin,

The PHY driver currently does not support asserting reset through device tree.

To assert reset and re-strap the pins, the register write is:
0x1F = 0x8000

Do I understand correctly that this register write needs to be implemented after system boots and DTS has loaded (due to PMIC change loading during boot)?

In this case, there needs to be a separate script or driver logic to perform this write after boot.

Thank you,

Evan

0 Benjamin Postma 10 months ago in reply to Evan Mayhew

Prodigy 70 points

Hi Evan,

thank you for your reply.

Evan Mayhew said:
The PHY driver currently does not support asserting reset through device tree.

That explains why it does not work. I removed the properties from my device tree.

Evan Mayhew said:
Do I understand correctly that this register write needs to be implemented after system boots and DTS has loaded (due to PMIC change loading during boot)?

I'm not sure if I have to reset the PHY at all. I only change the AVD voltage (2.5V to 1.8V). VDDIO is set to 1.8V from the beginning. Does this require a reset of the PHYs? My assumption is that the AVDD level detection has an undefined behaviour, since 2.5V is not supported, only 1.8V and 3.3V are.

Evan Mayhew said:
In this case, there needs to be a separate script or driver logic to perform this write after boot.

Now I wrote a script to change the level of the PHYs reset pin, if it is really required to reset the PHYs.

BR Benjamin

0 Evan Mayhew 10 months ago in reply to Benjamin Postma

TI__Mastermind 25148 points

Hi Benjamin,

For more robust operation, I recommend resetting the PHY if AVD or VDDIO levels change after the PHY powers.

Please let me know if you see any issues after asserting reset.

Thank you,

Evan

0 Benjamin Postma 10 months ago in reply to Evan Mayhew

Prodigy 70 points

Hi Evan,

okay, I will test it, and come back with my tests results on Monday.

Thanks so far.

BR Benjamin

0 Evan Mayhew 10 months ago in reply to Benjamin Postma

TI__Mastermind 25148 points

Sounds good, looking forward to results.

Thank you,

Evan

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DP83822I: Trigger a hard reset using a GPIO