TCAN4551-Q1: TCAN4551-Q1

Hello Amit,

The TCAN4551-Q1 uses the CAN FD Controller IP called MCAN developed by Bosch.  I would refer you to the M_CAN User's Manual (Link) for additional information on how to configure and use the MCAN features including timestamps for messages.  The only thing to note is that the TCAN4551-Q1 has added a register offset of 0x1000 to each MCAN register address.  Therefore as an example, the Control register is listed as 0x18 in the M_CAN User's Manual, but is actually 0x1018 in the TCAN4551-Q1.  Otherwise, all of the other information in the M_CAN User's Manual is applicable to the TCAN4551-Q1.

There is an “Internal” timestamp counter inside the M_CAN controller core that counts in multiples of CAN bit times. This is controlled in register 0x1020 (note this is an M_CAN register because of the 0x1000 offset). The Timestamp Counter Prescaler TCP[3:0] can be configured to count in multiples of 1 to 16 bit times as set with this register. The current Counter value can be read from register 0x1024 and at any time can be cleared or re-started by writing to 0x1024 if the “internal” counter has been configured for use. I will also note that I believe the device will use the Nominal Bit Times to count and does not count the FD bits which would overrun the counters too frequently.

The M_CAN controller allows for an alternative “External” timestamp counter to be used instead of the internal CAN bit time counter and it simply takes a 16 bit value from this external counter, but it doesn’t specify how this external counter should be implemented. The TCAN451-Q1 uses a standard divider off of the Host Clock frequency (crystal/clkin) that allows for a divided down clock value to be used as the time stamp. If you select a TSCC.TSS[1:0] value of “10” (register 0x1020) then this “external” timestamp counter will be used. And by “external” it simply means that it is external to the M_CAN Controller Core. But since this is a TCAN4551 specific feature, its prescaler is setup in register 0x0804. Notice the address offset indicates this is not an M_CAN core register. By default this register has a value of 0x02, which will yield a clock divider of 16. Writing the pescaler value to this register will clear and re-start the Counter. When this counter is configured for use, the counter’s current value can be read in register 0x1024 which is the same register as the Internal counter since there is only one counter that can be used at a time.

I will also note that you should add into the configuration routine a timestamp counter reset for which ever counter you chose to use so that once you start communicating on the CAN bus, you have a deterministic starting point for the counter values. Every time the counter wraps around, it will set an interrupt bit so that the MCU can keep track of how many times the counter has re-started. If this is important to you, I would suggest you have some form of secondary counter in the MCU to keep track of these wrap around interrupts which could be internally appended to the timestamp value captured from a message if the message is stored in some form of log.

Regards,

Jonathan