Tool/software:
Hello Team,
Our SoC supports a single lane PCIe Gen-2 lanes and we need to validate following features via same
1. NVMe support
2.WiFi/BT support via LGA module
3. A PCIe daughter card support
To achieve this, I am planning to implement a MUXing option for the PCIe lanes to derive the said feature support.
The table refers to how the MUX selection to be done for getting the said features
Can I proceed with this kind of implementation?
Is incorporation of multiple MUXes results in any kind of SI issues?
Can I use resistor bypassing option in place of MUX-2? Is this recommended?
